Router designs for elastic buffer on-chip networks

Abstract

This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes throughput by achieving a 42% reduction in cycle time and 20% reduction in occupied area by using look-ahead routing and replacing the three-slot output EBs in the baseline router of [17] with two-slot EBs. We also propose a singlestage router which merges the two pipeline stages to avoid pipelining overhead. This design reduces zero-load latency by 24% compared to the enhanced two-stage router if both are operated at the same clock frequency; moreover, the single-stage router reduces the required energy per transferred bit and occupied area by 29% and 30% respectively, compared to the enhanced two-stage router. However, the cycle time of the enhanced two-stage router is 26% smaller than that of the single-stage router.

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

“…A mesh-of-trees network was constructed from simple bundled-data routers for a CMP [20] that, same as our work, uses individually controlled latches for buffering. This is similar to the clocked elastic buffer concept [21]. The insertion of link pipeline buffers in an async NoC was explored and compared against a similarly-designed synchronous "elastic" network [22].…”

Evaluating Elastic Buffer and Wormhole Flow Control

“…Therefore, channels are used for buffering and router buffers are removed, eliminating the associated area and energy costs. EB networks trade off these savings for a wider datapath that increases their throughput and makes them more energy and area efficient than VC networks [12], [14]. Fig.…”

“…Further work has proposed improved EB router designs in the form of the enhanced two-stage and the single-stage routers [14]. The enhanced two-stage router, shown in Fig.…”

Floorplan-Aware High Performance NoC Design

“…Long links suffer from an excessive power consumption and large latency, that makes them costly or even unfeasible. To minimize the impact of long links, in [72][73][74] long links are replaced by elastic buffers, that is, buffered links where a trade-off between latency and power consumption is made, because a flit requires several hops to traverse an elastic buffer. In [75], authors focus on 3D technology as an ideal scenario to implant high-radix topologies because long 2D links evolve to short and power efficient 3D vias.…”

“…If not, those paths will become the critical paths of the HDC network design. In order to avoid the penalization of the whole system, for the design of the inter-region links we apply a pipelined approach, as proposed in [73]. In this sense, if the propagation time of a link is higher than the clock cycle imposed by maximum achievable frequency of DCs, then the link is pipelined and several clock cycles are spent for crossing a region.…”