NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers

Enam, S.K.; Abidi, A.A.

doi:10.1109/4.173103

Cited by 37 publications

(6 citation statements)

References 19 publications

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“…The third type of VCO shown is a variable-stage, or delay-interpolating (DI), VCO [5] [ Figure 2(c)]. This VCO consists of two delay lines of different lengths.…”

Section: Integrated Vco Design Techniquesmentioning

confidence: 99%

CMOS circuits for Gb/s serial data communication

Ewen¹,

Soyuer²,

Widmer³

et al. 1995

IBM J. Res. & Dev.

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The functional characteristics and design challenges associated with a variety of communication-related circuits are presented. These include the mixed-signal design and noise issues associated with high-speed clock generation and recovery for serial data communication. Hardware results are presented on the noise properties of common integrated voltage-controlled oscillator (VCO) circuits. introductionA key characteristic of ICs in many communication-related applications is the combination of analog circuits with digital logic, while maintaining maximum performance at minimum power and cost. This combination presents a number of challenges beyond basic circuit design issues, ranging from technology choice and simulation techniques to noise and crosstalk. This paper focuses on recent CMOS design work addressing these issues, with specific attention to the area of high-speed serial data communication.Serial baseband data links, whether using fiber-optic or coaxial cables, incorporate coders and decoders, highspeed multiplexors and demultiplexors, and low-speed clock synchronization, along with phase-locked loops for

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“…The third type of VCO shown is a variable-stage, or delay-interpolating (DI), VCO [5] [ Figure 2(c)]. This VCO consists of two delay lines of different lengths.…”

Section: Integrated Vco Design Techniquesmentioning

confidence: 99%

CMOS circuits for Gb/s serial data communication

Ewen¹,

Soyuer²,

Widmer³

et al. 1995

IBM J. Res. & Dev.

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“…A phase locked loop (Gardner 1979) is a common building block of several communication system related circuits, namely, FM demodulators (Jam and Moore 1977), frequency synthesizers (Klepser et al 2002), data clock recovery loops (Kim et al 1990, Enam andAbidi 1992) etc. Depending on the field of application, the properties of PLLs should have to be properly adjusted to get optimum performance of the system.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of a variable length ring oscillator and its use in PLL based systems

Mandal¹,

Sarkar²

2006

International Journal of Electronics

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This paper describes the properties of a multiplexer based variable length ring oscillator and the effects of using it as a voltage controlled oscillator (VCO) in a phase locked loop (PLL) based system. The application of the proposed VCO in a PLL used as an FM demodulator or as a frequency synthesizer has been examined and it has been shown that the length control facility of the VCO could be used for improving the performances of those systems. Hardware experimental results confirm the predictions regarding the performance enhancement.

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“…To compensate for the signal loss over the wire, such systems would require sophisticated equalizers to compensate for frequency dependent attenuation. In particular, since the I/O data rate equals the aggregate data rate and cannot be separately controlled in a system, the aggregate data rate is likely to be constrained to 40 Gbps/pin even in 65-nm CMOS technology (limited by of the CMOS technology [26], [27], where GHz forecasted by ITRS [28]). In contrast, our proposed interconnect schemes based on CDMA and FDMA can achieve aggregate data rate beyond 100 Gbps/pin given the availability of the same 65 nm technology (in principle, the maximum carrier frequency could approach ).…”

Section: System Benefitsmentioning

confidence: 99%

Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

Chang

Verbauwhede

Chien

et al. 2005

IEEE Trans. Electron Devices

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Abstract-Future inter-and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.

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NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers

Cited by 37 publications

References 19 publications

CMOS circuits for Gb/s serial data communication

CMOS circuits for Gb/s serial data communication

Characteristics of a variable length ring oscillator and its use in PLL based systems

Advanced RF/Baseband Interconnect Schemes for Inter- and Intra-ULSI Communications

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