Nibble-serial arithmetic processor designs via unfolding

Concurrent Architectures for VLSI Signal and Image Processing

“…We proposed a systematic unfolding technique to unfold bit-serial systems to digit-serial systems [5] [23] [27]. Furthermore, we also proposed a reverse folding technique to design hardware architectures for time-multiplexed DSP circuits [9] [28].…”

Design of low-power CIC decimation filter based on nibble serial arithmetic

“…For the problem where the internal bit width of the traditional CIC decimation filter is too high, this design innovatively proposes the overall architecture based on the nibble serial algorithm as shown in Figure 1. Including the clock control module and the CIC decimation filter realization structure [11,12]. The clock control module generates low frequency clock required by each module; the CIC decimation filter has 6 modules, namely: coding, integrator, decimator, comb filter, serial-to-parallel conversion, and truncation module.…”