A VLSI design methodology for distributed arithmetic

Burleson, Wayne; Scharf, Louis L.

doi:10.1007/bf00925468

Cited by 26 publications

(4 citation statements)

References 23 publications

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“…For instance, real-time audio signal processing involves converting analog audio to digital and applying effects such as reverb, equalization, and noise reduction using the DSP's ALU. DA-based ALU design [16] optimizes tasks such as convolution by replacing complex multiplications with precomputed partial products, reducing computational complexity and enabling quick processing for functions such as filtering and adaptive filtering [17]. The synergy of BRAM and a DA-driven ALU enhances performance, achieving high-quality audio effects and improvements across applications with demanding latency requirements.…”

Section: Proposed Methodsmentioning

confidence: 99%

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

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Section: Proposed Methodsmentioning

confidence: 99%

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Mohanarangam,

M Shirur

et al. 2023

Electronics

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“…Distributed arithmetic is an efficient multiplierless technique used for computing inner product when one of the input vectors is fixed [1][2][3][4][5] . Basically, DA is an algorithm that performs multiplication with a look-up table based scheme.…”

Section: Introductionmentioning

confidence: 99%

“…Here the LUT contains 16 locations i.e. 2 4 where 4 is the filter order. Therefore if we need to design and implement 70-tap FIR filter then the LUT size in this case will be 2 70 .…”

Section: Introductionmentioning

confidence: 99%

IFâ€“THEN Adder Application in Online DALUT Implementation

Eshtawie¹,

Othman²

2007

American J. of Applied Sciences

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This paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage of the basic DA architecture reported as the exponential growth of the LUT size with the number of input variables. The if-then adder was proposed in another work where it shows an efficient performance when compared with the well known ripple carry adder (RCA) and the carry lookahead adder (CLA). The online DALUT with the if-then adder was applied in designing 70-tap finite impulse response pulse shaping filter and some other different order FIR filters. The design was coded with Verilog hardware description language (verilog HDL) and synthesized using the Xilinx technology after being simulated with ModelSim 7.5g. The synthesis report shows that the design preference when using the if-then adder more efficient than in the case of the RCA and CLA adder. The maximum frequency reached with the design using the if-then adder was 85.095MHz, whereas, when using CLA and RCA adders it 77.936MHz and 77.042MHz respectively. Finally the design has been successfully downloaded to Virtex-II FPGA fg456 and tested with the TLA5201 logic analyzer.

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“…using the input carry in the shift-accumulator. The cell can be used to decrease or to increase the order of the lattice filter with the same A direct-form DA error model [9] is presented in (eq.13); r is the number of data samples partitions or memory partition. Furthermore, as a result of the 4-input LUT structures, the partition of the memories in the FPGA case is limited by r T/4 (T is the order of the filter).…”

Section: Bit-serial Da Error Modelmentioning

confidence: 99%