Integer addition is one of the most important operations in digital computers digital signal processing and. In fact the speed of adders affects the speed and performance of their processors. In digital signal processing, multiply and accumulate (MAC) unit plays an important role when designing digital filters. However, this role is doubled when multiplierless techniques such as distributed arithmetic (DA) are applied. In such techniques, the addition operation is the main scale when specifying some of the design parameters such as operation speed, design area, and the power consumed. This paper discusses the results obtained from the design analyzer for the proposed addition circuit together with the results obtained for the two most common adders i.e. the carry lookahead adder (CLA) and the ripple carry adder (RCA). The results obtained for the three different adders show that the proposed addition circuit has lowest area, lowest power consumption. On the other hand, the proposed adder has an operation speed higher than the RCA and a very close to the speed of the CLA.it is worth to mention here that the proposed design is based on the concept of applying a set of if-then rules. This set of rules calculates the out sum and carry in human-like way of processing.
This paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage of the basic DA architecture reported as the exponential growth of the LUT size with the number of input variables. The if-then adder was proposed in another work where it shows an efficient performance when compared with the well known ripple carry adder (RCA) and the carry lookahead adder (CLA). The online DALUT with the if-then adder was applied in designing 70-tap finite impulse response pulse shaping filter and some other different order FIR filters. The design was coded with Verilog hardware description language (verilog HDL) and synthesized using the Xilinx technology after being simulated with ModelSim 7.5g. The synthesis report shows that the design preference when using the if-then adder more efficient than in the case of the RCA and CLA adder. The maximum frequency reached with the design using the if-then adder was 85.095MHz, whereas, when using CLA and RCA adders it 77.936MHz and 77.042MHz respectively. Finally the design has been successfully downloaded to Virtex-II FPGA fg456 and tested with the TLA5201 logic analyzer.
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