A low power 10-bit 125-MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) based on MOS bucket-brigade devices (BBDs) is presented. A PVT insensitive boosted charge transfer (BCT) that is able to reject the charge error induced by PVT variations is proposed. With the proposed BCT, the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably. The prototype ADC based on the proposed BCT is realized in a 0.18 m CMOS process, with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm 2 . The prototype ADC achieves a spurious free dynamic range (SFDR) of 67.7 dB, a signal-to-noise ratio (SNDR) of 57.3 dB, and an effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are C0:5/ 0:3 LSB and C0:7/ 0:55 LSB, respectively.
Abstract:A process, voltage, temperature (PVT) insensitive boosted charge transfer (BCT) circuit for charge-domain (CD) pipelined analog-to-digital converters (ADC) is presented. The output charge of existing BCT varies extensively with PVT variation, leading to large common-mode charge errors in each differential BCT stage when used in CD pipelined ADCs. Therefore, complicate commonmode control circuits must be adopted to stabilize the common-mode charge of each stage, which consumes large power and chip area. The proposed BCT circuit employs a differential difference amplifier and a differential voltage reference to reject the charge errors caused by PVT variations. A 125-MSPS, 10-bit CD pipelined ADC without commonmode control circuit is implemented based on the proposed BCT, consuming only 27 mW from a 1.8 V supply.
The efficient and precise hardware implementations of tanh and sigmoid functions play an important role in various neural network algorithms. Different applications have different requirements for accuracy. However, it is difficult for traditional methods to achieve adjustable precision. Therefore, we propose an efficient-hardware, adjustable-precision and high-speed architecture to implement them for the first time. Firstly, we present two methods to implement sigmoid and tanh functions. One is based on the rotation mode of hyperbolic CORDIC and the vector mode of linear CORDIC (called RHC-VLC), another is based on the carry-save method and the vector mode of linear CORDIC (called CSM-VLC). We validate the two methods by MATLAB and RTL implementations. Synthesized under the TSMC 40 nm CMOS technology, we find that a special case AR∣VR(3,0), based on RHC-VLC method, has the area of 4290.98 μm2 and the power of 1.69 mW at the frequency of 1.5 GHz. However, under the same frequency, AR∣VC(3)(a special case based on CSM-VLC method) costs 3196.36 μm2 area and 1.38 mW power. They are both superior to existing methods for implementing such an architecture with adjustable precision.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.