New Triple Self-Aligned (SA3) Split-Gate Flash Cell with T-Shaped Source Coupling

Abstract

A new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance coupling capacitance between the source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V, which is characterized by a newly developed methodology for program vs disturb window characterization. For cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship between source coupling ratio (SCR) and the program/erase mechanism, an insightful discussion on the program and erase mechanisms for our split-gate flash cell is also shown in this paper.

Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness

“…Among different split-gate memory cells, the self-aligned split-gate flash cell has attracted much research interest for its fast erase, modular process and compatibility to CMOS process [5][6][7][8][9][10]. It uses floating gate (FG) tip enhanced poly-to-poly (FG to select gate) F-N tunnelling for erase, and source side hot electron injection for program [11,12].…”

On Application of Analytical Model for Drain-Coupling Split-Gate Flash: Analytical Solution to Source-Side Injection Multilevel Programming

“…The drain-coupling source-side injection (SSI) split-gate device has emerged as one of the fast-growing multilevel flash devices. 1) Its main benefits lie in the high programming efficiency and parallel programming capability of SSI programming, 2) no stress-induced leakage current (SILC)induced disturb or charge loss of poly-poly field-enhanced Fowler-Nordheim (FN) erase, 3) embedded applications of the highly compatible process with CMOS technology, 1) good scalability of the modulated process, 4) and better array efficiency, which results from an immunity to over programming and over erasing. 2) 256-M multilevel digital mass storage devices and 8 bit/cell analogue voice storage devices using the drain-coupling split-gate flash were reported.…”