New subthreshold concepts in 65nm CMOS technology

Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid; Peiravi, Ali; Aunet, Snorre; Cao, Tuan Vu

doi:10.1109/isqed.2009.4810287

Cited by 7 publications

(10 citation statements)

References 16 publications

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“…As it can be seen in Fig.3, in write cycle, when write=1, DATA=1, and WWL=0 (RDWL=0), node x is charged to VDD through three stacked PMOS transistors. As it is shown in [3], the three stacked PMOS has a much higher speed of three stacked NMOS transistors. So, in this case, write and read cycle are sperated and they are done, in two different modes due to WWL and RDWL signals.…”

Section: Sram Cellmentioning

confidence: 90%

See 1 more Smart Citation

Improved write margin 6T-SRAM for low supply voltage applications

Moradi

Wisland

Mahmoodi

et al. 2009

2009 IEEE International SOC Conference (SOCC)

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In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.

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Section: Sram Cellmentioning

confidence: 90%

“…But for lower supply voltage or for sub-threhold design, M7-M10 should be upsized too much. In [3] it's shown that for lower supply voltages, PMOS transistors are faster than NMOS's. So, in this case, it's shown that if we use the PMOS transistors to implement the write path, the write cycle is improved.…”

Section: Sram Cellmentioning

confidence: 99%

Improved write margin 6T-SRAM for low supply voltage applications

Moradi

Wisland

Mahmoodi

et al. 2009

2009 IEEE International SOC Conference (SOCC)

Self Cite

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“…The second problem in stacking is the reduction in current due to stacked devices which results in loss of speed in subthreshold region. This, however, can be offset by body biasing [7]. For example, in [7] authors proposed complementary hybrid latch flip-flop (CHLFF) for ultralowpower applications and Forward Body Bias (FBB) was used to increase the speed of the PMOS (p-channel MOSFET) stacked network.…”

Section: Challenge 1: Pvt Variationmentioning

confidence: 99%

“…This, however, can be offset by body biasing [7]. For example, in [7] authors proposed complementary hybrid latch flip-flop (CHLFF) for ultralowpower applications and Forward Body Bias (FBB) was used to increase the speed of the PMOS (p-channel MOSFET) stacked network. It was found that reducing the supply voltage to 0.3 V in an NMOS (n-channel MOSFET) stacked flip-flop (FF) causes some failures in corners.…”

Section: Challenge 1: Pvt Variationmentioning

confidence: 99%

Recent Subthreshold Design Techniques

Radfar

Shah²,

Singh³

2012

Active and Passive Electronic Components

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Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

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“…For example, in the super-threshold region PMOS is usually sized twice as big as NMOS to achieve equal PMOS and NMOS current or rise and fall delay. But it has been found that in the near/sub-threshold region PMOS needs to be upsized heavily compared to NMOS in order to achieve equal rise and fall delay [8][9] [10]. This is because the current becomes exponentially related to the threshold voltage when VDD approaches the threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library

Zhou

Jayapal

Busze

et al. 2011

Proceedings of the 48th Design Automation Conference

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We have investigated the impact of inverse narrow width effect on the threshold voltage and drain current in the near/sub-threshold region at three technology nodes (90 nm, 65 nm and 40 nm) and proposed a new sub-threshold device sizing method which is inverse-narrow-width-effect-aware to reduce the gate area, power consumption and delay. We applied the proposed sizing method in designing a 40 nm sub-threshold standard cell library. Compared with the sub-threshold standard cell library designed using the conventional sizing method, the proposed library has up to 20% less delay, up to 34% less power consumption and up to 47% less area. We used the proposed library for designing a digital base-band processor and achieved a total power consumption of around 5 μw with 6 MHz at 0.5 V, which is 17% better than the counterpart design.

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New subthreshold concepts in 65nm CMOS technology

Cited by 7 publications

References 16 publications

Improved write margin 6T-SRAM for low supply voltage applications

Improved write margin 6T-SRAM for low supply voltage applications

Recent Subthreshold Design Techniques

A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library

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