This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct modulated transmitter transmits OOK signal with 0 dBm peak power, and it consumes 2.59 mW with 50% OOK. The transmitter front-end supports up to 10 Mbps. The transmitter digital baseband enables digital pulse-shaping to improve spectrum efficiency. The super-regenerative receiver front-end supports up to 5 Mbps with -75 dBm sensitivity. Including the digital part, the receiver consumes 715 μW at 1 Mbps data rate, oversampled at 3 MHz. At the system level the transceiver achieves PER=10 (-2) at 25 meters line of site with 62.5 kbps data rate and 288 bits packet size. The transceiver is integrated in an electrocardiogram (ECG) necklace to monitor the heart's electrical property.
In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72μW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9μW.
We have investigated the impact of inverse narrow width effect on the threshold voltage and drain current in the near/sub-threshold region at three technology nodes (90 nm, 65 nm and 40 nm) and proposed a new sub-threshold device sizing method which is inverse-narrow-width-effect-aware to reduce the gate area, power consumption and delay. We applied the proposed sizing method in designing a 40 nm sub-threshold standard cell library. Compared with the sub-threshold standard cell library designed using the conventional sizing method, the proposed library has up to 20% less delay, up to 34% less power consumption and up to 47% less area. We used the proposed library for designing a digital base-band processor and achieved a total power consumption of around 5 μw with 6 MHz at 0.5 V, which is 17% better than the counterpart design.
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