New security threats against chips containing scan chain structures

Abstract

Insertion of scan chains is the most common technique to ensure observability and controllability of sequential elements in an IC. However, when the chip deals with secret information, the scan chain can be used as back door for accessing secret (or hidden) information, and thus jeopardize the overall security. Several scan-based attacks on cryptographic functions have been described and showed the need for secure scan implementations. These attacks assume a single scan chain. However the conception of large designs and restrictions in terms of test costs may require the implementation of many scan chains and additional test infrastructures for test response compaction. In this paper, we present a new generic scan attack that covers a wide range of industrial test infrastructures, including spatial response compressors.

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor

“…In [1], the authors claim that identification of these KFFs in the scan design is crucial for successful recovery of the encryption key. However, this has been contradicted in later works presented by Da Rolt et al [4], [5].…”

“…Although scan-chain Designfor-Test (DFT) offers the highest testability, they are prone to scan-based side channel leakages which may help an intruder to perform a non-invasive attack on secure chips to extract secret information such as cryptographic keys from secure hardware implementations. In fact, there are works available in the literature which exploit this property, and they are referred to as scan-based side channel attacks [3], [4], [5]. However, these works do not consider any X-tolerant or X-masking logic which is widely used in industrial test compression schemes, and gravely affects the applicability and running time of these attacks.…”

Crypto-Test-Lab for security validation of ECC co-processor test infrastructure

“…Performance of the scan-path countermeasure CTL platform has been used to evaluate the [11] countermeasure. It is meant for scan-path protection and thus the attack has been mounted to discover k using the [15] methodology but applied in the ECC core, as described by A. Das in [16].…”

“…Once the unit starts he can interrupt it at any iteration of the Montgomery algorithm, see Figure 3, switch to test mode and scan-out the content of Q 0 and Q 1 . He also assumes that scan-paths are compressed, as described in [15], and therefore uses the parity evaluation of the output bits as a feedback for carrying out the attack.…”

An Efficient Technique to Protect AES Secret Key from Scan Test Channel Attacks

“…To achieve better productivity SoC designers are forced to reuse design modules from external sources of IP of which security is not well verified. To prevent the security failure in one module from being cascaded through test subsystems of chips, security enhanced test access mechanisms are addressed to escape from the threat posed by untrustworthy cores [14,15]. A protection scheme is proposed for serial JTAG channels which are prone to be downgraded by any threat of a malicious chip in a JTAG chain [16].…”