2008
DOI: 10.1109/aero.2008.4526472
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New Reprogrammable and Non-Volatile Radiation Tolerant FPGA: RTA3P

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Cited by 24 publications
(8 citation statements)
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“…Previous work of accurate SET pulse electrical injection shows a strong SET pulse-width modulation when SET pulse traverses logic gates [8]. In addition, it has been concluded that the SET pulse width at the input of the storage element is strictly dependent on the propagation and type of traversed logic gates [9].…”
Section: Related Workmentioning
confidence: 94%
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“…Previous work of accurate SET pulse electrical injection shows a strong SET pulse-width modulation when SET pulse traverses logic gates [8]. In addition, it has been concluded that the SET pulse width at the input of the storage element is strictly dependent on the propagation and type of traversed logic gates [9].…”
Section: Related Workmentioning
confidence: 94%
“…In addition, it has been concluded that the SET pulse width at the input of the storage element is strictly dependent on the propagation and type of traversed logic gates [9]. This SET pulse width is also dependent on the routing structure of the used technology [8]. In [10], an Accurate Analysis of SET effects on Flash-based FPGA System-on-a-Chip for Satellite Applications S. Azimi, B.…”
Section: Related Workmentioning
confidence: 99%
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“…In this way SETs influence the processing speed of the clock signal dependent system [9]. Furthermore, it is well known, that errors originating from SETs are strongly dependent on the internal clock frequencies [10]. As charged particles can hit the electronic system anytime and anywhere no countermeasures except for full radiation shielding is possible.…”
Section: Single Event Transientsmentioning
confidence: 99%
“…While for SEE, the primary concern resides in the upset of its registers (state of the flip-flop) due to a particle hit, resulting in the disruption of the normal operation of the FPGA-design [Rezgui et al, 2007a[Rezgui et al, & 2007b. The new Radiation-Tolerant ProASIC3 (RT ProASIC3 or RT3P), sharing the same silicon of the Low-Power A3PL FPGAs is hardened for TID and SEE by software means in a transparent manner to the user [Rezgui et al, 2008a]. The Single Event Transients (SET) tolerance is hardened by single or duplication filtering [Shuler et al, 2005& 2006, Balasubramanian et al, 2005, Baze et al, 2006, Mavis & Eaton, 2007, Rezgui et al, 2007a and Single Event Upsets (SEU) are hardened by TMR or Error Detection and Correction (EDAC) to soft error rates less than 10 -10 upsets/bit-day and LET th larger than 40 MeV•cm 2 /mg for clock frequency up to 100 MHz.…”
Section: Introductionmentioning
confidence: 99%