New redundant logic design concept for high noise and low voltage scenarios

Garcia-Leyva, Lancelot; Andrade, D.; Fernandez, S. Gomez; Calomarde, Antonio; Moll, Francesc; Rubio, Antonio

doi:10.1016/j.mejo.2011.09.007

Cited by 3 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In particular, the MRF framework used feedback of the satisfiability constraints of a gate's function to reinforce correct behavior. More recently, Turtle Logic (TL) has been proposed to achieve noise immunity by exploiting port redundancy and coherence analysis of the redundant data [6]. Both these approaches show a greatly improved immunity to noise compared to standard implementations; however, they carry significant area overhead which can have a substantial negative impact on power dissipation and delay.…”

Section: Noise-immune Circuit Designmentioning

confidence: 99%

See 1 more Smart Citation

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

Donato

Cremona

Jin

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Nanoscale circuits operating at sub-threshold voltages are affected by growing impact of random telegraph signal (RTS) and thermal noise. Given the low operational voltages and subsequently lower noise margins, these noise phenomena are capable of changing the value of some of the nodes in the circuit, compromising the reliability of the computation. We propose a method for improving noise-tolerance by selectively applying feed-forward reinforcement to circuits based on use of existing invariant relationships. As reinforcement mechanism, we used a modification of the standard CMOS gates based on the Schmitt trigger circuit. SPICE simulations show our solution offers better noise immunity than both standard CMOS and fully reinforced circuits, with limited area and power overhead.

show abstract

Section: Noise-immune Circuit Designmentioning

confidence: 99%

“…A number of techniques to improve noise-immunity of nanoscale circuits have been proposed, many of them based on adding redundant logic to the circuit (e.g., [17], [12], [6]). However, one of the main drawbacks of these solutions is the relatively high transistor count overhead required to achieve reasonable levels of noise immunity.…”

Section: Introductionmentioning

confidence: 99%

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

Donato

Cremona

Jin

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…In order to solve the problem of reliability against noise, several solutions have been published recently [27] [28], but none of them address the SET issue. One of the proposals designed to solve the problem of noise tolerance is based on the theory of Markov Random Field (MRF) [26] .…”

Section: Introductionmentioning

confidence: 99%

“…One of the proposals designed to solve the problem of noise tolerance is based on the theory of Markov Random Field (MRF) [26] . Moreover, the Turtle concept [27] uses redundancy in the inputs, and the common feature for both differential solutions is the high noise immunity, but this requires a large number of transistors and has a proportional increase in susceptible nodes to SET.…”

Section: Introductionmentioning

confidence: 99%

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Calomarde

Amat

Moll

et al. 2014

Microelectronics Reliability

View full text Add to dashboard Cite

Abstract-In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. This technology's independent design style achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. We propose two alternatives for this methodology in 7nm FinFET, and, to check the accuracy of our proposal, we compare them with previous techniques for hardening radiation at the transistor level against a Single Event Transient. Simulation results show that the proposed method has a higher soft error tolerance capability than existing methods as well as better noisy immunity.

show abstract

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Ghaffarishad

Mohammadzadeh

Ghaznavi‐Ghoushchi

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90-nm CMOS standard technology show that the proposed logic improves the average powerdelay product by about 40% for the attempted benchmarks. KEYWORDS adaptive voltage scaling (AVS), digital logic design, power-performance tunable logic, pseudodynamic logic | INTRODUCTIONIn the past few decades, digital circuit performance improved rapidly; mostly enabled by aggressive improvement of transistor performance. The exponential decrease in transistor feature sizes accompanied by exponential increase in transistor-switching speed has led to incredible computing power in today's integrated circuit. However, these devices have serious limitations on power dissipation. Obtaining energy efficiency and low peak power while maintaining computational performance is one of the primary goals in contemporary processor design.Transistor variability in very-large-scale integrated circuit. Increases with the very-large-scale integration process technology scaling trend, as smaller transistors have higher circuit parameter uncertainties. On the other hand, the off-leakage current of sub-100 nm processes is considerable. 1 In other words, in the sub-100 nm processes, the off-leakage power is a significant portion of the total power consumed by a circuit. For example, at the 90-nm technology node, leakage power may make up 42% of total power. 2 Beyond the circuit topology, the major factor in control and reduction of leakage power and current is the MOS transistors threshold voltage altering. Threshold voltage is subject of 2 different kinds of controllability: design-time and run-

show abstract

New redundant logic design concept for high noise and low voltage scenarios

Cited by 3 publications

References 11 publications

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Contact Info

Product

Resources

About