2014
DOI: 10.1016/j.microrel.2013.12.018
|View full text |Cite
|
Sign up to set email alerts
|

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Abstract: Abstract-In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. This technology's independent design style achieves SET m… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2019
2019
2021
2021

Publication Types

Select...
3
2

Relationship

0
5

Authors

Journals

citations
Cited by 12 publications
(2 citation statements)
references
References 30 publications
(31 reference statements)
0
2
0
Order By: Relevance
“…In combinational circuits, SEUs can be induced as an additional current which is injected at selected nodes and then propagates through the logic elements and can give rise to soft errors. 27 In this work, we evaluate the effect of NBTI in combination with the soft error radiation hardening enhancement of integrated CMOS circuits. To this end, firstly the soft error analysis of a two-input NAND gate is performed at different operating temperatures and a total stress time of up to 3 years.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…In combinational circuits, SEUs can be induced as an additional current which is injected at selected nodes and then propagates through the logic elements and can give rise to soft errors. 27 In this work, we evaluate the effect of NBTI in combination with the soft error radiation hardening enhancement of integrated CMOS circuits. To this end, firstly the soft error analysis of a two-input NAND gate is performed at different operating temperatures and a total stress time of up to 3 years.…”
Section: Introductionmentioning
confidence: 99%
“…The aforementioned SEU is the most common type for a single event effect (SEE) occurring in storage elements (latches and memory cells), which can lead to a flip of the logic state of a circuits' output. In combinational circuits, SEUs can be induced as an additional current which is injected at selected nodes and then propagates through the logic elements and can give rise to soft errors 27 …”
Section: Introductionmentioning
confidence: 99%