2011
DOI: 10.1016/j.sse.2011.06.037
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New mechanism of plasma induced damage on CMOS image sensor: Analysis and process optimization

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Cited by 18 publications
(5 citation statements)
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“…The memory characteristics, including the program/erase speed, charge retention, and endurance, were significantly improved by the incorporation of fluorine atoms, resulting in a built-in electric field in the Gd 2 O 3 nanostructure. However, defects are inevitably introduced into the dielectric matrix when a plasma is applied, owing to plasma damage resulting from energetic ion bombardment and ultraviolet (UV) irradiation [25][26][27]. This damage may counterbalance the passivation effect because of additional defects induced by the plasma.…”
Section: Introductionmentioning
confidence: 99%
“…The memory characteristics, including the program/erase speed, charge retention, and endurance, were significantly improved by the incorporation of fluorine atoms, resulting in a built-in electric field in the Gd 2 O 3 nanostructure. However, defects are inevitably introduced into the dielectric matrix when a plasma is applied, owing to plasma damage resulting from energetic ion bombardment and ultraviolet (UV) irradiation [25][26][27]. This damage may counterbalance the passivation effect because of additional defects induced by the plasma.…”
Section: Introductionmentioning
confidence: 99%
“…IC design rules include considerations to mitigate damage to gate oxides by antenna effects (charging during plasmabased processing) [67], [68]. Post-processing steps that employ plasma can cause similar damage, which can be avoided by depositing a metal layer beforehand to electrically short all the exposed CMOS connections.…”
Section: Damage To Circuits During Post-processingmentioning
confidence: 99%
“…In modern process technologies, PID is believed to significantly impact the performance of MOSFETs and other devices such as memory, 48,49) image sensor, 50,51) power device, 52,53) and optical device. 54) Approaches for suppressing PID in the field of plasma design should be carried out in combination with device and circuit designs, since higher performance is required with low ULSI chip cost and a rapid time-to-market.…”
Section: Introductionmentioning
confidence: 99%