New high voltage SOI device structure eliminating substrate bias effects

Based on the concept of critical field EI,C II. THE ENDIF CONCEPT approaching for dielectric layer, the ENDIF (ENhanced Vertical breakdown voltage (VBv) of 501 devices is supported Dlelectric layer Field) principle for SOt HV devices is by Si layer and dielectric layer, and the latter is greater one. Then proposed for the first time, from which three approaches to enhance fileld of dielectric layer EI for increasing vertical enacgF1imoefetveoicrseVV.Bednth EDeanc e rtical concept of EIC approaching for dielectric layer, by ENDIF, three breakdown voltage VB,v are presented: approaches are given to increase EI which are enhancing field in silicon Esc at the interface of Si/dielectric layer by the critical field in silicon Esc at the interface of using thin silicon layer. Considering the threshold energy of S l b u t silicon ETI the expression of ESC for both thick and thin Si Sim lem trin interf c using lo w k layer is derived firstly and shown that ESC increases sharply dieletriayerr6es shown inuFig. 1. with decreasing of thin Si layer thickness ts and Es,c and EI c for SiO2 are up to 141V/pm and 422V/pm at ts=0.1pm, Take the threshold energy ET into account for electron respectively; (raise a structure of buried dielectrics layer multiplying in thin Si layer[8], we derive the with low permittivity (LK) and variable permittivity (VK) ®implement the interface charges between silicon and h dielectric layer, from which a new dielectric structure with ___i DT SOI is proposed, and E1 of 300V/pm is experimentally -+ P -(tin) obtained. By ENDIF, the formula E and VB,vare given, which m m m n m n. A are meet good with 2D simulation and experimental results. ... .... With ENDIF, several conventional SO devices are well explained. P

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“…Vd -q n Itj 1 (8) Fig.6 gives some 2D simulative results by MEDICI and experimental results [1,[12][13] for comparison with analytical results…”

Section: Esmentioning

confidence: 99%

The Rule of Field Enhancement for Buried Dielectric Layer of SOI High Voltage Devices

Zhang

Luo

et al. 2007

2007 International Conference on Communications, Circuits and Systems

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“…10(a), the BV of the ERT remains constant as V BG varies from 0 to 100 V, effectively shielding the impact of the BG bias. This shielding effect does not require any modification of the BOX structure, compared with prior arts in [6] and [7]. The reason is that substantial inversion holes are induced at the n-SOI/BOX interface when V SB = V app − V BG ≥ V TH,BG , where V SB is the potential difference between source and the BG.…”

Section: B Bg Effectmentioning

confidence: 99%

“…SOI devices introduce a back-gate (BG) bias effect. References [6] and [7] use a SIPOS layer to eliminate the BG bias effect. However, these works focus on nLDMOS.…”

mentioning

confidence: 99%

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Zhou

Luo

et al. 2014

IEEE Trans. Electron Devices

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A low specific ON-resistance (R ON,sp ) silicon-oninsulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFFstate, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low R ON,SP and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and R ON,SP . Compared with the p-top SOI pLDMOS, the proposed device reduces the R ON,SP by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.Index Terms-Back gate (BG), breakdown voltage (BV), p-channel LDMOS (pLDMOS), reduced surface field (RESURF), specific ON-resistance.

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“…(1), as the V sb increases. The MOS diode portion consists of n + -cathode, nlayer, buried oxide and the substrate [7]. Therefore, the cath- Fig.…”

Section: Accumulatiom Regionmentioning

confidence: 99%

“…For a power diode built by SOI technology, the influence of the substrate bias on the breakdown voltage is eliminated by inserting a semi-insulating polycrystalline silicon layer (SIPOS) [6]. But the SIPOS layer is not compatiable with the standard power IC technology, because the leakage current is increased by the SIPOS over silicon interface traps [7,8].…”

Section: Introductionmentioning

confidence: 99%

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer

Ho¹,

Chien²,

Liao³

et al. 2008

TOEEJ

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An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter to affect the strong inversion condition in the back MOS capacitor of the new SOI diode. The optimum design of LDBL thickness for the SOI diode was 2.65 μm. Furthermore, the breakdown capability has been improved 11%.

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New high voltage SOI device structure eliminating substrate bias effects

Cited by 14 publications

References 0 publications

The Rule of Field Enhancement for Buried Dielectric Layer of SOI High Voltage Devices

The Rule of Field Enhancement for Buried Dielectric Layer of SOI High Voltage Devices

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer

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