New Efficient Reverse Converters for 8n-bit Dynamic Range Moduli Set

Abstract

This paper proposes two efficient residue to binary converters on a new three-moduli set using the Chinese Remainder Theorem. The proposed reverse converters are adder based and memoryless. In comparison with other moduli sets with similar dynamic range, the new schemes out-perform the existing schemes in terms of both hardware cost and relative performance.

A New Efficient Residue to Binary Converter for (5n+2)-bit Dynamic Range Moduli Set

“…These inherent properties make RNS very suitable to achieve a fast digital signal processing (DSP) systems including intensive computations like digital filtering, convolutions, correlations, Discrete Fourier Transform (DFT) computations, Fast Fourier Transform (FFT) computations and Direct Digital Frequency (DDF) synthesis [2]. However, RNS has not found a widespread usage in general purpose computing due to some difficult operations including overflow detection, magnitude comparison, sign detection, moduli selection, and conversion from decimal/binary to RNS and most especially the vice visa, [3], [4], [5]. Of many of these numerous RNS difficult operations, Data conversion is very critical.…”

“…Data Conversion, which is usually based on either the Chinese Remainder Theorem (CRT) [6]], [7] [8] or the Mixed Radix Conversion (MRC) [9] can be categorized into forward and reverse conversions. The forward conversion is conversion of binary/decimal to a residue form while the reverse conversion involves converting the RNS number into binary or decimal [10], [5]. Relatively, reverse conversion is more complex.…”

Efficient RNS Reverse Converter using New Chinese Remainder Theorem I and the Moduli Set {24n, 22n+1, 2n+1, 2n-1}

“…[7] proposed vertical and horizontal extensions which enabled it to increase the dynamic range of the moduli set 2 , 2 − 1, 2 + 1, 2 − 2 +1 2 + 1, 2 + 2 +1 2 + 1 from 5 bits to 8 + 1 bits. [1] and [8]…”

“…1 respectively. The moduli sets in [1] have a dynamic range of 5 bits and that of [8] has a dynamic range of 8 bits. Because of the high dynamic range, the moduli set in [7] and [8] are more appropriate for DSP applications.…”

“…The work of [8] proposed two hardware architectures based on the Chinese remainder theorem and the moduli set 2 2 − 1, 2 4 , 2 2 + 1 . One architecture is optimized for cost efficiency (CE) and the other is optimized for speed efficiency (SE).…”