Efficient RNS Reverse Converter using New Chinese Remainder Theorem I and the Moduli Set {24n, 22n+1, 2n+1, 2n-1}

Abstract

Residue number system (RNS) is a promising technology for high speed, power efficient and fault tolerant hardware design. The reason is that in RNS, arithmetic operations are performed in parallel, thus reducing delays due to carry operations. Additionally, RNS computations are faster than binary computations because of the reduced wordlength due to modulo operations. Despite the advantages of RNS, its performance depends on the moduli set and the reverse conversion algorithm used to convert the residue numbers back to binary form. There is therefore the need to select the moduli set and the reverse conversion algorithm carefully so that the performance of the RNS hardware is not overshadowed by reverse conversion overheads. This paper proposes an 8n bit moduli set 2 4 , 2 2 + 1, 2 + 1, 2 − 1 and a reverse conversion hardware architecture based on the new Chinese remainder theorem I(new CRT I). Compared to existing hardware architecture, the proposed architecture shows good balance between the hardware cost efficiency and speed efficiency. Secondly, the proposed architecture outperforms existing systems in terms of cost-delay square (Δ 2).