New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

Priya, G. Lakshmi; Balamurugan, N. B.

doi:10.1016/j.aeue.2018.11.037

Cited by 49 publications

(19 citation statements)

References 22 publications

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“…In this paper, we analyze the subthreshold swing of the asymmetric JLDG MOSFET for the dielectric constant range from 3.9 to 80, such as SiO2, Al2O3, Y2O3, HfO2/ZrO2, La2O3, and TiO2 which Priya et al [24] used to analyze the transfer characteristics of the junctionless transistor. In addition, the potential distribution model of the asymmetric junction-based double gate MOSFET presented by Ding et al is modified to apply for the asymmetric JLDG MOSFET [25].…”

Section: Introductionmentioning

confidence: 99%

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Jung

2021

IJECE

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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Section: Introductionmentioning

confidence: 99%

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Jung

2021

IJECE

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“…Amin et al analyzed the gate tunneling currents in the symmetrical junctionless DGMOSFETs using SiO2/high-k stacked gate oxide films [25]. Priya et al presented the subthreshold swing of the junctionless DGMOSFET when the dielectric materials of gate oxide films were SiO2, Al2O3, Y2O3, HfO2/ZrO2, La2O3, and TiO2 with the relative permittivities of from 3.9 to 80 [26]. In this paper, we analyze the on-off current ratio according to channel dimension, oxide thickness, and permittivity of oxide film for the junctionless DGMOSFET with stacked gate oxide, using potential distribution model that can be used in symmetrical as well as asymmetrical JLDG MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Jung

Kim

2021

IJECE

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The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO2/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 104 or less is shown for SiO2, but the on-off current ratio for TiO2 (k=80) increases to 107 or more.

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“…Impact of geometrical variability's on the performance of JLTFET and Junctionless hetero structure TFETs (HJLTEFT) is investigated and proposed pocket oxide narrower source side HJTFETs (PNS-HJTFETs) for better performance [22]. The effect of the gate dual material (DMG) and gate engineering approach on the performance of DGJL-TFET is studied [23][24][25]. Comprehensive analysis on the 20nm HJLTFETs with high-k gate oxide material is presented [26].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Double Gate Junctionless Tunnel Field Effect Transistor: RF Stability Perspective

Raju

Sivasankaran

2019

IJACSA

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This paper investigates the RF Stability performance of the Double Gate Junctionless Tunnel Field Effect Transistor (DGJL-TFET). The impact of the geometrical parameter, material and bias conditions on the key figure of merit (FoM) like Transconductance (g m ), Gate capacitance (C gg ) and RF parameters like Stern Stability Factor (K), Critical Frequency (f k ) are investigated. The analytical model provides the relation between f k and small signal parameters which provide guidelines for optimizing the device parameter. The results show improvement in ON current, g m , f t and f k for the optimized device structure. The optimized device parameters provide guidelines to operate DGJL-TFET for RF applications.

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New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

Cited by 49 publications

References 22 publications

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Performance Analysis of Double Gate Junctionless Tunnel Field Effect Transistor: RF Stability Perspective

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