2011
DOI: 10.1103/physrevstab.14.102802
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New digital low-level rf system for heavy-ion synchrotrons

Abstract: In the scope of the Facility for Antiproton and Ion Research (FAIR) project, several new synchrotrons and storage rings will be built. The existing heavy-ion synchrotron SIS18 has to be upgraded to serve as an injector for the FAIR accelerators. All this imposes new requirements on the low-level rf (LLRF) systems. These requirements include fast ramping modes, arbitrary ion species, and complex beam manipulations such as dual-harmonic operation, bunch merging/splitting, barrier bucket operation, or bunch compr… Show more

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Cited by 18 publications
(11 citation statements)
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“…The FIR filter currently used to control the SIS18 synchrotron [15] is implemented on a digital signal processor (DSP) on a custom-designed board described in [11]. The FIR filter already stretches the capabilities of the DSP and so we do not anticipate that the DSP will be an appropriate implementation technology for the FGM.…”
Section: Algorithm 1 Fast Gradient Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…The FIR filter currently used to control the SIS18 synchrotron [15] is implemented on a digital signal processor (DSP) on a custom-designed board described in [11]. The FIR filter already stretches the capabilities of the DSP and so we do not anticipate that the DSP will be an appropriate implementation technology for the FGM.…”
Section: Algorithm 1 Fast Gradient Methodsmentioning
confidence: 99%
“…The FIR filter already stretches the capabilities of the DSP and so we do not anticipate that the DSP will be an appropriate implementation technology for the FGM. However, the hardware described in [11] also includes a high-end FPGA, allowing the possibility of a custom hardware implementation of Algorithm 1. Consequently, we implemented the FGM of Algorithm 1 in a hardware description language, VHDL, and performed timing simulations using the TimeQuest Timing Analyzer that is provided as part of the Altera suite of FPGA design tools.…”
Section: Algorithm 1 Fast Gradient Methodsmentioning
confidence: 99%
“…Für die Strahlregelung im Synchrotron SIS18 wurde eine maß-geschneiderte Hardware entwickelt [25], welche digitale Signalprozessoren (DSP) und einen programmierbaren Logikbaustein (field programmable gate array, FPGA) umfasst. Das bisher verwendete FIR-Filter (vgl.…”
Section: Fpga-basierte Implementierung Des Mpcunclassified
“…5. A complete description of the rf systems is given in [22]. An amplitude modulator drives the accelerating cavity that produces the voltage U RF with amplitudeÛ 0 and amplitude and phase modulations u 1 and u 2 ; cf.…”
Section: A Rf Setup Of Sis18mentioning
confidence: 99%
“…For the implementation of the filter, a DSP system is used consisting of analog narrowband preprocessing, automatic gain control, analog-to-digital converters, FPGA, DSPs, and digital-to-analog converters. More details on this hardware can be found in [22], p. 6. The FIR filter is realized on a DSP system with floating point arithmetic, enabling almost arbitrary coefficients.…”
Section: A Rf Setup Of Sis18mentioning
confidence: 99%