New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata

Pudi, Vikramkumar; Sridharan, K.

doi:10.1109/tcsii.2012.2213356

Cited by 43 publications

(22 citation statements)

References 14 publications

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“…Besides the high level logic aspects above detailed, it is worth underlining that the performances achieved by QCA-based circuits strictly depend on the applied layout policies that directly influence the number of clock phases because of the interconnections. The multilayer strategy, adopted in most of the existing QCA designs [3,[7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26], has the advantage of leading to interconnections shorter than those required by applying the co-planar strategy, with a significant improvement in terms of computational time. Usually, multilayered QCA structures use the main layer for both logic gates and wires, whereas the additional layers are exploited only to implement bridges for wire crossings.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Recently the emerging technology based on quantum-dot cellular automata (QCA) has received a great deal of attention, and several solutions have been proposed to design efficient logic circuits, such as multiplexers [1-3], adders [4][5][6][7][8][9][10][11], multipliers [12][13][14][15][16][17][18] and comparators [19][20][21][22][23][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

“…">INTRODUCTIONRecently the emerging technology based on quantum-dot cellular automata (QCA) has received a great deal of attention, and several solutions have been proposed to design efficient logic circuits, such as multiplexers [1-3], adders [4][5][6][7][8][9][10][11], multipliers [12-18] and comparators [19][20][21][22][23][24][25][26].The QCA nanostructure originally demonstrated in [27] uses a square cell with four quantum dots and two free electrons as the basic element to realize both logic structures and interconnections. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate.…”

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confidence: 99%

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Design of efficient QCA multiplexers

Cocorullo

Corsonello

Frustaci

et al. 2015

Circuit Theory & Apps

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A new methodology to realize efficient multiplexers using quantum-dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan-in, by adding in the worst-case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. INTRODUCTIONRecently the emerging technology based on quantum-dot cellular automata (QCA) has received a great deal of attention, and several solutions have been proposed to design efficient logic circuits, such as multiplexers [1-3], adders [4][5][6][7][8][9][10][11], multipliers [12-18] and comparators [19][20][21][22][23][24][25][26].The QCA nanostructure originally demonstrated in [27] uses a square cell with four quantum dots and two free electrons as the basic element to realize both logic structures and interconnections. The free electrons can tunnel through the dots within the cell, but, owing to Coulombic repulsion, they can lead to only two possible stable states, also named polarizations, that are associated with the binary states 1 and 0. Even though adjacent cells interact through electrostatic forces and tend to align their polarizations, QCA cells do not have intrinsic data flow directionality. The latter is provided by means of four clock signals clk x (with x ranging from 0 to 3), shifted by 90°from each other, that are progressively associated to the cells within a QCA design [28,29]. This clock scheme, named the zone clocking scheme, makes the QCA designs intrinsically pipelined, because each clock zone behaves like a D-latch.The fundamental logic gates inherently available within the QCA technology are the inverter and the majority gate (MG); non-elementary digital modules are designed combining instances of these basic gates and exploiting an efficient zone clocking scheme . The design of complex gates, such as multiplexers (MUXes), is not actually straightforward, and proper strategies have to be adopted at both logic and layout levels to improve performance and area behaviors.Large fan-in multiplexers (i.e. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. This paper is focused on the design of efficient QCA-based large fan-in MUXes and proposes a novel approach that smartly exploits the majority logic function

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Section: Background and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Design of efficient QCA multiplexers

Cocorullo

Corsonello

Frustaci

et al. 2015

Circuit Theory & Apps

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“…In this case the overall area is reduced with respect to [11], but maintaining the same computational path. By applying the decomposition method [14], the computational paths of the CLA and the CF A are reduced to 7 + 210g2 (n/8) MGs and one inverter and to (nil) + 3 MGs and one inverter, respectively.…”

Section: Existing Qca Addersmentioning

confidence: 99%

Design and implementation of Arithmetic Logic Unit (ALU) using modified novel bit adder in QCA

Kanimozhi

Shankar

2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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Moore's law states that the number of transistors that could be integrated into a single die would grow exponentially with time. Thus this causes increasing computational complexity of the chip and physical limitations of devices such as power consumption, interconnect will become very difficult. According to recent analysis the minimum limit for transistor size may be reached. Thus, it may not be possible to continue the rule of Moore's law and doubling the clock rate for every three years. So in order to overcome this physical limit of CMOS-VLSI design an alternative approach is Quantum dot Cellular Automata (QCA). In ALU adder plays a vital role. In this survey a binary adder is taken for analysis and a new adder is designed based upon QCA technology.This modified novel bit adder is implemented into ALU structure. The aim of this proposed technique is that to reducing number of majority gates used in the design.This will lead to reduce number of QCA cells so that total area of ALU circuit can be minimized compare to previous designs. It also achieves reduced power consumption and high speed performances than all other existing ALU design which uses normal full adder ..

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“…More number of gates used in the circuit mounts the delay and also area occupied by the system. This was a disadvantageous system [9]. To prevail over the above mentioned problems a couple of Boolean equations were formulated in the Section IV.…”

Section: Introductionmentioning

confidence: 99%

Stubby delay comparator in QCA: The C-Gate

Babu

Bharadwaja

Neelima

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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Quantum Dot Cellular Automata (QCA) is an appealing technology for designing very stubby power and high response digital Circuits. QCA is an computational model of Quantum theory. QCA Circuits are the corporal implementation of Cellular Automata by utilizing Quantum behavior. QCA is based on interplay rules amidst the cells placed on a tracery. A new gate called Comparison Gate shortened as C-Gate has been put forward in this work. The work is to explain the C-Gate and check its efficiency. The proposed gate can be extended for a lot many bits depending on the usage. The regular counter parts in QCA give very high delay as to C-Gate. This paper totally is opus of the C-Gate both theoretically and simulated version of it. The gate is simulated on Xilinx 14.2i and compared with other gates.

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New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata

Cited by 43 publications

References 14 publications

Design of efficient QCA multiplexers

Design of efficient QCA multiplexers

Design and implementation of Arithmetic Logic Unit (ALU) using modified novel bit adder in QCA

Stubby delay comparator in QCA: The C-Gate

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