New combination of damage control techniques using SEN's single-wafer implanters

Ninomiya, S.; Hirokawa, S.; Sato, Fumiaki; Okamoto, Yasuharu; Yumiyama, Toshio; Inai, K.; Funai, Akira; Shinozuka, M.; Kato, Koji; Ishikawa, M.; Ebisu, Satoshi; Kudo, Tetsuya; Kagawa, T.; Fukui, Taichiro; Morita, Tatsuro; Suetsugu, Noriyuki; Tsukihara, Mitsukuni; Fuse, G.; Ueno, Kazuyoshi

doi:10.1109/iwjt.2011.5970006

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…[8] A significant reduction in implantation-induced crystal damage results in device performance improvement. [9] Normal implant processes can lead to strain relaxation caused by implant damage. Strain relaxation can be also reduced with cryo-implants.…”

Section: Molecular/cluster Implantmentioning

confidence: 99%

“…The next generation of sub-nano CMOS imposes a new set of challenges for the source and drain portions of the device, such as stringent junction depth control requirements with ever-increasing dopant activation, [1][2][3][4][5] elimination of residual structural defects, [8][9][10][11] and improvement/preservation of process-induced strain. [40][41][42] Many innovations are needed in the doping and deposition processes forming the source and drain in order to resolve the above issues.…”

Section: Introductionmentioning

confidence: 99%

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Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Song

Blatchford

2011

Electron. Mater. Lett.

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TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

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Section: Molecular/cluster Implantmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%