New CMOS shallow junction well FET structure (CMOS-SJET) for low power-supply voltage

Yoshimura,; Matsuoka,; Kakumu,

doi:10.1109/iedm.1992.307504

Cited by 13 publications

(4 citation statements)

References 4 publications

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“…In this work, we use two of 3-layered MLP (inputhidden-output layers) as shown in fig.2 because the structure is simple enough to control non-linearity function by changing the number of perceptrons in the hidden layer. By using these two MLPs, we model two functions of transistor, F power (1) and F delay (2), which respectively output log-scaled power log(O power ) and delay log(O delay ) of a device from given input log-scaled vector log(I p ) of manufacturing parameters p, where power and delay, or power delay products (PDP) are figure-of-merits for digital logic applications [12].…”

Section: B Neural-network-based Modeling For Power and Delay Predictionmentioning

confidence: 99%

“…Random initial values of manufacturing parameters were generated under the uniform distribution in a reasonable range, i.e., from I min p to I max p of (9) where I min p = 0.95×reference value in table 1 (-5%) and I max p = 1.05×reference value in table 1 (+5%). The small deviation τ = 2 × 10 −8 was used for calculating accurate numerical gradient (11) and the learning rate γ = 10 3 was used for update equation (12) for fast convergence. T P DP = 0, T G = 10 −5 , and T dx = 10 −5 were used for termination condition (8).…”

Section: Performance Evaluation Of Automatic Manufacturing Parametmentioning

confidence: 99%

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Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing

et al. 2020

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An optimal design of semiconductor device and its process uniformity are critical factors affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible malfunctioning in semiconductor manufacturing. Two main tasks in optimal device design for semiconductor manufacturing, i.e., parameter optimization and modeling, have been typically used either to characterize the devices by understanding how each parameter affects the device performances or to calibrate the parameters for SPICE circuit simulation. However, there still remains limitations in describing the relationship between all manufacturing parameters and figure-of-merits using several simple equations human experts can utilize. Even with the best model currently available, the optimal design of semiconductor device heavily relies on experiences of human experts and deals with time-consuming ad-hoc trials and non-holistic approaches. In this paper, we propose a new approach for data-based accurate electrical modeling of transistor, which is the most fundamental unit device of semiconductor, and fast optimization of its manufacturing parameters. Instead of the previous analytic approaches, finding finite equations derived from semiconductor physics, we utilize machine learning technique and neural networks to find appropriate modeling functions from data pairs of parameters and figure-of-merits. And for given desired figure-of-merits, we find optimal manufacturing parameters in holistic manner by using the learned functions of neural networks and fast gradient-based optimization method. Experimental results show that our neural-network-based-model directly estimate figure-of-merits with competitive accuracy and that our holistic optimization technique accurately and rapidly adapts the manufacturing parameters to meet desired figure-of-merits.

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Section: B Neural-network-based Modeling For Power and Delay Predictionmentioning

confidence: 99%

Section: Performance Evaluation Of Automatic Manufacturing Parametmentioning

confidence: 99%

Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing

et al. 2020

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“…Furthermore, if we apply gradient descent [ 7,8 ] to a single NN (one multilayer perceptron [MLP]) to optimize the input for low output in sparse data space, the optimal input has output deviation depending on the training indices of the NN. For example, Table 1 contains five input sets optimized by five MLPs with different training/validation datasets and five outputs, the power‐delay product (PDP) of the 29‐stage ring oscillator, [ 9 ] estimated by the MLPs. Each MLP outputs a much lower PDP than the other MLPs when the input is optimized by the MLP itself.…”

Section: Introductionmentioning

confidence: 99%

Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development

Yun

Jang

et al. 2023

Advanced Intelligent Systems

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Herein, novel neural network (NN) methods that improve prediction accuracy and reduce output variance of the optimized input in the gradient method for cross‐sectional data are proposed, and the variability evaluation approach of optimized inputs in the semiconductor process is suggested. Specifically, electrical parameter measurements (EPMs) and power‐delay product of industrial high‐k metal gate DRAM peripheral 29‐stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (R2) by 5.6–15.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0–81.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.

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“…The basic idea of pseudo depletion layer beneath the source and drain in SDODEL MOSFET is similar to shallow junction well transistor (SJETs) [4,5], pseudo SOI [2] or SODEL FET [3] which have a special p-n junction beneath the channel region in the substrate. Almost all such devices are intended to achieve fully depleted (FD) channel CMOS operation except SODEL FET, which achieves partially depleted (PD) channel.…”

Section: Introductionmentioning

confidence: 99%