New CML latch structure for high speed prescaler design

Usama, Muhammad; Kwaśniewski, T.

doi:10.1109/ccece.2004.1347586

Cited by 12 publications

(5 citation statements)

References 3 publications

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“…The Tx module [7] converts the 5 Gbps serial data to the Current Mode Logic (CML) signals as the final outputs. The 2.5 GHz clock required by both the multi-phase generator and the 2:1 module is provided by a high-speed clock receiving module (clock Rx) [8].…”

Section: Jinst 17 C01072 2 Design Of the 5 Gbps Serializer Chipmentioning

confidence: 99%

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

et al. 2022

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This paper presents the design and the test results of a low-power 5 Gbps 10:1 serializer chip with the self-check function based on a standard 130 nm CMOS technology. This serializer chip adopts a multi-level design scheme with a combination of the multi-phase structure (5:1 module) in the low data rate part and the tree structure (2:1 module) in the high date rate part. The high data rate 2:1 module adopts a latch-induced latency control circuit to ensure the timing margin across corners. The serializer chip has been fully tested, wide-open 5 Gbps output eye diagram has been captured, and the logic function has also been verified. The measured power consumption of the whole chip is 42 mW including Rx/Tx, and the power consumption of the serializer core is around 12.1 mW.

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Section: Jinst 17 C01072 2 Design Of the 5 Gbps Serializer Chipmentioning

confidence: 99%

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

et al. 2022

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“…Another technique used here to increase the output voltage is a capacitive divider [15]. It uses a capacitive voltage division network to decrease the swing at the bases of the cross-coupled transistors, with respect to the tank voltage swing (C 1 and C 2 ).…”

Section: Capacitive Dividermentioning

confidence: 99%

RF and mixed signal circuits for a DVB-H receiver

Khemchandani

Pino

López-Morillo

et al. 2010

Analog Integr Circ Sig Process

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This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcastinghandheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 lm BiCMOS process.

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“…Conventionally for a divider application two identical CM L latches are used in a master-slave configuration. It is possible to sim plify the usual C M L latch clocking struc ture by employing a single clock transistor pair to switch the current between the sample and hold pair o f the master and slave latches [34]. This new configuration uses a single bias current source for both latches.…”

Section: Master-slave Combined CML Latchmentioning

confidence: 99%

“…In a conventional C M L latch having a single current source this is not possible, so a dual current source C M L latch was suggested [29]. In the proposed mas ter-slave combined latch technique [34], the current difference is accomplished by using…”

Section: Urrent M Ode L O G Ic Latch a N D P Resca Le R D Esign O Pmentioning

confidence: 99%

Current mode logic latch and prescaler design optimization in 0.18um CMOS technology

Usama¹

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New CML latch structure for high speed prescaler design

Cited by 12 publications

References 3 publications

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

RF and mixed signal circuits for a DVB-H receiver

Current mode logic latch and prescaler design optimization in 0.18um CMOS technology

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