New architecture for RFFT calculation

Hidalgo-López, José A.; Tejero, J.C.; Fernández, José‐Jesús; Herruzo, E.; Gago, A.

doi:10.1049/el:19941289

Cited by 4 publications

(5 citation statements)

References 2 publications

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“…(1) (i) = [i n01 ; 11 1;i 1 ; i n ]: (2) In some cases, it will be convenient to divide the base r representation of data into several ordered fields of digits i = (; ; ); = 11 12]: (4) Definition 3: The exchange operator (i);(j) exchanges the ith digit of field with the jth digit of field . As an example, (1);(1) (; ; ) = [ a 111 2 1 ][][ c 2 1 ]: (5) Hereafter, the operator (1);(1) will be denoted by ; for simplicity.…”

Section: Definitionmentioning

confidence: 99%

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Area-efficient architecture for Fast Fourier transform

Hidalgo

López

Argüello

et al. 1999

IEEE Trans. Circuits Syst. II

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We present an area-efficient parallel architecture that implements the constant-geometry, in-place Fast Fourier Transform. It consists of a specific-purpose processor array interconnected by means of a perfect unshuffle network. For a radix r transform of N = r n data of size D and a column of P = r p processors, each processor has only one local memory of N=rP words of size rD, with only one read port and one write port that, nevertheless, make it possible to read the r inputs of a butterfly and write r intermediate results in each memory cycle. The address generating circuit that permits the in-place implementation is simple and the same for all the local memories. The data flow has been designed to efficiently exploit the pipelining of the processing section with no cycle loss. This architecture reduces the area by almost 50% of other designs with a similar performance.

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Section: Definitionmentioning

confidence: 99%

“…Vector quantization [4] is an efficient image coding technique, achieving low bit rates, i.e., lower than 1 bit per pixel. Vector quantization is described as …”

Section: Introductionmentioning

confidence: 99%

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Area-efficient architecture for Fast Fourier transform

Hidalgo

López

Argüello

et al. 1999

IEEE Trans. Circuits Syst. II

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“…According to this, N/2 − 1 outputs of the FFT are redundant and can be removed. Most approaches [11], [27], [31] obtain either the frequencies with…”

Section: Proposed Algorithm For the Computation Ofmentioning

confidence: 99%

“…These specific approaches describe programs based on removing the redundancies of the CFFT when the input is real, and can be used to efficiently compute the RFFT in a DSP (Digital Signal Processor) or in in-place architectures [31]. A memory-based or in-place architecture consists of a memory and a processing unit.…”

Section: Introductionmentioning

confidence: 99%

A Pipelined FFT Architecture for Real-Valued Signals

Garrido

Parhi

Grajal

2009

IEEE Trans. Circuits Syst. I

119

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Abstract-This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the Decimation In Time (DIT) and Decimation In Frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2.Finally, as in previous works, when calculating the RFFT the output samples are obtained in a different order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

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A Real-time TAM-BP Imaging Algorithm for Subsurface Imaging Radar

Lei

Huang

2005 IEEE International Conference on Ultra-Wideband

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New architecture for RFFT calculation

Cited by 4 publications

References 2 publications

Area-efficient architecture for Fast Fourier transform

Area-efficient architecture for Fast Fourier transform

A Pipelined FFT Architecture for Real-Valued Signals

A Real-time TAM-BP Imaging Algorithm for Subsurface Imaging Radar

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