Neurotech for Neuroscience: Unifying Concepts, Organizing Principles, and Emerging Tools

Silver, Rae; Boahen, Kwabena; Grillner, Sten; Kopell, Nancy; Olsen, Kathie L.

doi:10.1523/jneurosci.3575-07.2007

Cited by 96 publications

(68 citation statements)

References 92 publications

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“…This approach is analogous to the manner in which software is used to program and compile computational processes in general purpose digital computers, except that the underlying neuromorphic hardware is radically different from digital ones in both system concept and electronic implementation. The approach is sufficiently general to be used on a wide range of electronic neural networks that have reconfigurable synaptic weights and reprogrammable connectivity (6,7,61).…”

Section: Discussionmentioning

confidence: 99%

“…So far, research emphasis has been on developing largescale neural-like electronic systems (6)(7)(8). However, the concepts and methods for installing the dynamics necessary to express cognitive behaviors on these substrates are relatively poorly developed, mainly because the deep question of how biological brains install cognition on their neural networks remains open.…”

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confidence: 99%

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Synthesizing cognition in neuromorphic electronic systems

Neftci

Binas

Rutishauser

et al. 2013

Proc. Natl. Acad. Sci. U.S.A.

127

122

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The quest to implement intelligent processing in electronic neuromorphic systems lacks methods for achieving reliable behavioral dynamics on substrates of inherently imprecise and noisy neurons. Here we report a solution to this problem that involves first mapping an unreliable hardware layer of spiking silicon neurons into an abstract computational layer composed of generic reliable subnetworks of model neurons and then composing the target behavioral dynamics as a "soft state machine" running on these reliable subnets. In the first step, the neural networks of the abstract layer are realized on the hardware substrate by mapping the neuron circuit bias voltages to the model parameters. This mapping is obtained by an automatic method in which the electronic circuit biases are calibrated against the model parameters by a series of population activity measurements. The abstract computational layer is formed by configuring neural networks as generic soft winner-take-all subnetworks that provide reliable processing by virtue of their active gain, signal restoration, and multistability. The necessary states and transitions of the desired high-level behavior are then easily embedded in the computational layer by introducing only sparse connections between some neurons of the various subnets. We demonstrate this synthesis method for a neuromorphic sensory agent that performs real-time context-dependent classification of motion patterns observed by a silicon retina.decision making | sensorimotor | working memory | analog very large-scale integration | artificial neural systems U nlike digital simulations, in which the dynamics of neuronal models are encoded and calculated on general purpose digital hardware, "neuromorphic" emulations express the dynamics of the neural systems directly on an analogous physical substrate (1). Digital simulations have the advantage that they can be exactly and reliably programmed using numerical operations of very high precision. However, they suffer the disadvantage that they are cast on abstract binary electronic circuits whose operation is entirely divorced from the physical processes being simulated. Consequently, such simulations do not readily advance our understanding of how biological neural systems are able to attain their extraordinary physical performance, using only large numbers of apparently unreliable, slow, and imprecise neural components, a problem first recognized by von Neumann more than a half century ago (2). Furthermore, the reliability of digital systems comes at high cost of the circuit complexity necessary for the orchestration of communication and processing, an overhead that declares itself also in the costs of system construction and power dissipation (3).The alternative, neuromorphic, approach to information processing strives to capture in complementary metal-oxide semiconductor (CMOS) very large-scale integration (VLSI) electronic technology the more distributed, asynchronous, and limited precision nature of biological intelligent systems (1, 4).†, ‡ Research...

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Section: Discussionmentioning

confidence: 99%

mentioning

confidence: 99%

Synthesizing cognition in neuromorphic electronic systems

Neftci

Binas

Rutishauser

et al. 2013

Proc. Natl. Acad. Sci. U.S.A.

127

122

View full text Add to dashboard Cite

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“…At the same time, recent advent of near-nanoscale three-dimensional CMOS processes and integrated circuit technology will likely further decrease device dimensions and overall chip sizes in near future (44,98). Such neurotechnological advances provide a new dimension for understanding how the brain works and for transitioning this knowledge to practical applications (99).…”

Section: Discussionmentioning

confidence: 99%

A biophysically-based neuromorphic model of spike rate- and timing-dependent plasticity

Rachmuth

Shouval²,

Bear

et al. 2011

Proc. Natl. Acad. Sci. U.S.A.

172

149

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Current advances in neuromorphic engineering have made it possible to emulate complex neuronal ion channel and intracellular ionic dynamics in real time using highly compact and powerefficient complementary metal-oxide-semiconductor (CMOS) analog very-large-scale-integrated circuit technology. Recently, there has been growing interest in the neuromorphic emulation of the spike-timing-dependent plasticity (STDP) Hebbian learning rule by phenomenological modeling using CMOS, memristor or other analog devices. Here, we propose a CMOS circuit implementation of a biophysically grounded neuromorphic (iono-neuromorphic) model of synaptic plasticity that is capable of capturing both the spike rate-dependent plasticity (SRDP, of the Bienenstock-Cooper-Munro or BCM type) and STDP rules. The iono-neuromorphic model reproduces bidirectional synaptic changes with NMDA receptor-dependent and intracellular calcium-mediated long-term potentiation or long-term depression assuming retrograde endocannabinoid signaling as a second coincidence detector. Changes in excitatory or inhibitory synaptic weights are registered and stored in a nonvolatile and compact digital format analogous to the discrete insertion and removal of AMPA or GABA receptor channels. The versatile Hebbian synapse device is applicable to a variety of neuroprosthesis, brain-machine interface, neurorobotics, neuromimetic computation, machine learning, and neural-inspired adaptive control problems.iono-neuromorphic modeling | rate-based synaptic plasticity | silicon neuron | subthreshold microelectronics | VLSI circuit L earning and memory are emergent animal behaviors governed by activity-dependent neuronal adaptation rules in response to changing environments. A putative neuronal mechanism of learning and memory is Hebbian synaptic plasticity (1)-the adaptive modification of excitatory synaptic strength following paired activation of the pre-and postsynaptic neurons. Two classic paradigms for the induction of Hebbian synaptic plasticity in the mammalian hippocampus and neocortex are rate-based plasticity (2-4) [herein referred to as spike-rate-dependent plasticity (SRDP)] and spike-timing-dependent plasticity (STDP) (5-7). The SRDP induction protocols control presynaptic firing rate in order to vary the sign and magnitude of synaptic plasticity (8): a high-frequency (20-100 Hz) train of presynaptic pulses results in long-term potentiation (LTP) of the synaptic strength, whereas a low-frequency (1-5 Hz) train results in long-term depression (LTD). These protocols are consistent with the theoretical learning rule (BCM rule) proposed by Bienenstock, Cooper, and Munro (9), in which the sign and magnitude of synaptic plasticity are controlled solely by postsynaptic activity as determined by presynaptic firing rate: low postsynaptic activity weakens synaptic efficacy and high postsynaptic activity strengthens it. By contrast, the STDP induction protocol stipulates that precise timing of preand postsynaptic activities determines the direction and strength of synaptic pl...

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“…However, to meet the requirement of real-time interaction with the environment, some of the recently proposed VLSI design solutions that operate only on "accelerated time" scales (i.e., in which unit of real time is "simulated" in hardware two or three orders of magnitude faster), are not suitable [7], [8]. Similarly, neural VLSI solutions that focus on large-scale systems simulations are not ideal, as they compromise the low-power or compactness requirements [9]- [12]. In this paper we propose a compact full-custom VLSI device that comprises low-power sub-threshold analog circuits and asynchronous digital circuits to implement networks of spiking neurons with programmable synaptic weights [13], [14].…”

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confidence: 99%

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

Moradi

Indiveri

2014

IEEE Trans. Biomed. Circuits Syst.

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Abstract-We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 32 SRAM cells, 4 32 synapse circuits and 32 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.Index Terms-Address event representation (AER), analog/digital, asynchronous, circuit, event-based, learning, neural network, neuromorphic, programmable weights, real-time, sensory-motor, silicon neuron, silicon synapse, spike-timing dependent plasticity (STDP), spiking, static random access memory (SRAM), synaptic dynamics, very large scale integration (VLSI).

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Neurotech for Neuroscience: Unifying Concepts, Organizing Principles, and Emerging Tools

Cited by 96 publications

References 92 publications

Synthesizing cognition in neuromorphic electronic systems

Synthesizing cognition in neuromorphic electronic systems

A biophysically-based neuromorphic model of spike rate- and timing-dependent plasticity

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

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