An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

Abstract

Abstract-We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 32 SRAM cells, 4 32 synapse circuits and 32 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.Index Terms-Address event representation (AER), analog/digital, asynchronous, circuit, event-based, learning, neural network, neuromorphic, programmable weights, real-time, sensory-motor, silicon neuron, silicon synapse, spike-timing dependent plasticity (STDP), spiking, static random access memory (SRAM), synaptic dynamics, very large scale integration (VLSI).

Decision making and perceptual bistability in spike-based neuromorphic VLSI systems

“…We use an analog/digital mixed signal VLSI neuromorphic device that contains implementations of silicon neurons and synapses using subthreshold analog circuits, and asynchronous memory and communication blocks [18] (see Fig. 1a).…”

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems

“…This module takes care of “compiling” the neural network definition into a configuration table for the routing of the AER events in the setup according to the available hardware resources. For example, the API can apply methods for converting the LUT representation of the connectivity into dedicated routing schemes, such as hierarchical, multi-cast, broadcasting or tag-based schemes (Northmore and Elias, 1998; Furber et al, 2006; Merolla et al, 2007; Joshi et al, 2010; Moradi and Indiveri, 2014) or for appending additional parameters such as delays or probabilistic spiking in the configuration of the routers.…”

Towards a Neuromorphic Vestibular System

“…Each neuron has a dendritic input which comprises 32 programmable synapses with four bit resolution weights stored in a local asynchronous Static Random Access Memory block, as well as 8 synapses with spike-based plasticity circuits. The programmable synapse circuits and asynchronous Static Random Access Memory (SRAM) block have been already presented in [30], [31], while the learning synapses have been described in [32]. In here we focus on the system-level aspects and point the interested reader to the above mentioned publications for details on the individual circuits.…”