Current advances in neuromorphic engineering have made it possible to emulate complex neuronal ion channel and intracellular ionic dynamics in real time using highly compact and powerefficient complementary metal-oxide-semiconductor (CMOS) analog very-large-scale-integrated circuit technology. Recently, there has been growing interest in the neuromorphic emulation of the spike-timing-dependent plasticity (STDP) Hebbian learning rule by phenomenological modeling using CMOS, memristor or other analog devices. Here, we propose a CMOS circuit implementation of a biophysically grounded neuromorphic (iono-neuromorphic) model of synaptic plasticity that is capable of capturing both the spike rate-dependent plasticity (SRDP, of the Bienenstock-Cooper-Munro or BCM type) and STDP rules. The iono-neuromorphic model reproduces bidirectional synaptic changes with NMDA receptor-dependent and intracellular calcium-mediated long-term potentiation or long-term depression assuming retrograde endocannabinoid signaling as a second coincidence detector. Changes in excitatory or inhibitory synaptic weights are registered and stored in a nonvolatile and compact digital format analogous to the discrete insertion and removal of AMPA or GABA receptor channels. The versatile Hebbian synapse device is applicable to a variety of neuroprosthesis, brain-machine interface, neurorobotics, neuromimetic computation, machine learning, and neural-inspired adaptive control problems.iono-neuromorphic modeling | rate-based synaptic plasticity | silicon neuron | subthreshold microelectronics | VLSI circuit L earning and memory are emergent animal behaviors governed by activity-dependent neuronal adaptation rules in response to changing environments. A putative neuronal mechanism of learning and memory is Hebbian synaptic plasticity (1)-the adaptive modification of excitatory synaptic strength following paired activation of the pre-and postsynaptic neurons. Two classic paradigms for the induction of Hebbian synaptic plasticity in the mammalian hippocampus and neocortex are rate-based plasticity (2-4) [herein referred to as spike-rate-dependent plasticity (SRDP)] and spike-timing-dependent plasticity (STDP) (5-7). The SRDP induction protocols control presynaptic firing rate in order to vary the sign and magnitude of synaptic plasticity (8): a high-frequency (20-100 Hz) train of presynaptic pulses results in long-term potentiation (LTP) of the synaptic strength, whereas a low-frequency (1-5 Hz) train results in long-term depression (LTD). These protocols are consistent with the theoretical learning rule (BCM rule) proposed by Bienenstock, Cooper, and Munro (9), in which the sign and magnitude of synaptic plasticity are controlled solely by postsynaptic activity as determined by presynaptic firing rate: low postsynaptic activity weakens synaptic efficacy and high postsynaptic activity strengthens it. By contrast, the STDP induction protocol stipulates that precise timing of preand postsynaptic activities determines the direction and strength of synaptic pl...

No abstract

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.