Neighbor-cell assisted error correction for MLC NAND flash memories

Abstract

Continued scaling of NAND flash memory to smaller process technology nodes decreases its reliability, necessitating more sophisticated mechanisms to correctly read stored data values. To distinguish between different potential stored values, conventional techniques to read data from flash memory employ a single set of reference voltage values, which are determined based on the overall threshold voltage distribution of flash cells. Unfortunately, the phenomenon of program interference, in which a cell's threshold voltage unintentionally changes when a neighboring cell is programmed, makes this conventional approach increasingly inaccurate in determining the values of cells. This paper makes the new empirical observation that identifying the value stored in the immediate-neighbor cell makes it easier to determine the data value stored in the cell that is being read. We provide a detailed statistical and experimental characterization of threshold voltage distribution of flash memory cells conditional upon the immediate-neighbor cell values, and show that such conditional distributions can be used to determine a set of read reference voltages that lead to error rates much lower than when a single set of reference voltage values based on the overall distribution are used. Based on our analyses, we propose a new method for correcting errors in a flash memory page, neighborcell assisted correction (NAC). The key idea is to re-read a flash memory page that fails error correction codes (ECC) with the set of read reference voltage values corresponding to the conditional threshold voltage distribution assuming a neighbor cell value and use the re-read values to correct the cells that have neighbors with that value. Our simulations show that NAC effectively improves flash memory lifetime by 33% while having no (at nominal lifetime) or very modest (less than 5% at extended lifetime) performance overhead.

RowHammer and Beyond

“…There have been recent large-scale field studies a well as small-scale controlled studies of real memory errors on real devices and systems, showing that both DRAM and NAND flash memory technologies are becoming less reliable [82, 78, 98-100, 77, 93, 28, 27, 74, 73, 17, 25, 79, 84, 80]. As detailed experimental analyses of real DRAM and NAND flash chips show, both technologies are becoming much more vulnerable to cell-to-cell interference effects [82,55,26,22,20,17,21,81,72,23,28,27,79,80], data retention is becoming significantly more difficult in both technologies [69,47,70,49,89,31,46,75,25,18,71,17,21,19,81,48,28,27,74,73,82,79], and error variation within and across chips is increasingly prominent [70,63,30,29,17,21,64,[51]…”

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

“…Wearout increases the inaccuracy during program and erase operations, thereby increasing the number of P/E cycling errors. Cell-to-cell program interference errors [15,16] are another type of write-induced error that increases the threshold voltage of a cell and thereby increases the RBER, when an adjacent cell in another wordline is being programmed. Since parasitic capacitance coupling exists between cells within close proximity of each other, when a high programming voltage is applied on one cell, the capacitance coupling adds charge to the transistors of the adjacent cells, increasing the program interference errors.…”

“…First, we perform a detailed characterization and analysis of three error characteristics that are drastically different in 3D NAND flash memory than in planar NAND flash memory: layer-to-layer process variation (Section 4.2), early retention loss (Section 4.3), and retention interference (Section 4.4). In addition to identifying new error sources in 3D NAND flash memory, we use our methodology to corroborate and quantify 3D NAND error characteristics that are a result of error sources that were previously identified in planar NAND flash memory, including retention loss [6-9, 11, 23, 80], P/E cycling [9,11,14,64,80,81], program interference [4,9,11,15,16,80], read disturb [5,9,11,81], and process variation [13,84]. We summarize our findings for these error types in Section 4.5, and provide detailed results on our characterization of these previously-identified error sources in Appendix A.…”

“…To mitigate retention loss in 3D NAND flash memory, we propose ReMAR, a new technique that tracks the retention time information within the SSD controller and uses our new retention loss model (see Section 5.2) to predict and apply the optimal read reference voltage that is fine-tuned to the retention time of the data (Section 6.3). To mitigate retention interference, we propose ReNAC, which is adapted from neighbor-cell assisted correction (NAC) [16], an existing technique originally designed to reduce program interference in planar NAND flash memory, to also account for retention interference in 3D NAND flash memory (Section 6.4).…”

“…In this way, LI-RAID distributes the less reliable pages within each chip across different RAID groups, thereby avoiding the formation of significantly less reliable RAID groups that bottleneck SSD reliability. Note that, since the order of RAID group number is different in each flash chip, the LI-RAID layout may potentially violate the program sequence recommended by flash vendors, where wordlines within each flash block must be programmed in order to minimize harmful program interference [9,15,16,77]. For example, in Chip 2 in Figure 13, Wordline 3 (Groups 2 and 3) is programmed after Wordline 2 (Groups 0 and 1).…”