Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications

Gupta, Manish; Hu, Vita Pi‐Ho

doi:10.1109/led.2020.2969210

Cited by 26 publications

(11 citation statements)

References 25 publications

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“…The way charges and voltages have been calculated is now explained: for a given effective gate voltage V gate(ef f ) , the total charge density of ferroelectric Q is known either from (20) or (22). Next, introducing Q in (7) and using equation (1), the applied gate voltage V gate is finally obtained.…”

Section: A Recalling Jlfet Core Equationsmentioning

confidence: 99%

“…3.b. To summarize, the total charge density of ferroelectric is now known in all regions of operation from depletion (20) to accumulation (22), resulting in a relationship between V gate(ef f ) and V gate . Furthermore, we know the link between V gate(ef f ) and the mobile charge density in the channel, and so the relationship between V gate and Q m , giving finally the expected I D − V gate dependence.…”

Section: A Recalling Jlfet Core Equationsmentioning

confidence: 99%

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Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Rassekh

Sallèse

Jazaeri

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels. Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

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Section: A Recalling Jlfet Core Equationsmentioning

confidence: 99%

Section: A Recalling Jlfet Core Equationsmentioning

confidence: 99%

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Rassekh

Sallèse

Jazaeri

et al. 2020

IEEE J. Electron Devices Soc.

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“…Introduction: Junctionless transistors (JLT) are regarded as one of the most promising candidates to suppress short channel effects as metaloxide-semiconductor field-effect transistors (MOSFETs) scale into subnanometer era [1][2][3]. JLT turns off under depletion condition and on under flatband condition.…”

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confidence: 99%

Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate

Zhou

Yang

et al. 2023

Electronics Letters

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A novel junctionless gate‐all‐around (GAA) transistor with ultrathin nanosheet GAA channel and self‐aligned raised source/drain (RSD) is successfully designed and fabricated on void embedded silicon on insulator (VESOI) substrate through a much simpler fabrication process. Devices with as thin as 13‐nm nanosheet GAA channel thickness exhibit excellent electrical characteristics: on/off current ratio of 106 and on‐state drive current of 58 µA/µm. Although the parasitic planar channel component still exists, the device performance is decisively dominated by the GAA channel, and further boosted by the junction‐free bulk conduction mechanism and the self‐aligned RSD structure.

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“…7 In the recent past, JL devices have been explored for analog/RF, 8 sub-60 mV decade −1 switching, 9,10 sensing, 11 ultra-low power, 12 and neuromorphic 13 applications. Recently, various research groups [14][15][16][17] have reported the performance of NCJL devices. While the JL devices are actively considered as potential candidates at lower technology nodes, the higher sensitivity towards channel doping limits the usability of JL devices.…”

mentioning

confidence: 99%

“…The occurrence of positive V fe induced by net positive channel charge density at V gs = 0 V is the characteristic feature of NCJL devices. 17 This positive V fe leads to negative internal gate voltage (V int ) at V gs = 0 V, which facilitates the efficient channel depletion (or lower I off ) in a NCJL device designed with a relatively heavily doped channel. Figure 7b shows the behavior of the internal gate voltage (V int ) with varying V gs .…”

mentioning

confidence: 99%

Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors

Gupta

2021

ECS J. Solid State Sci. Technol.

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In this work, we report on the impact of channel doping on the performance of junctionless (JL) and negative capacitance (NC) JL devices designed with a gate length (L g) of 18 nm. Results showcase that NCJL devices exhibit negative internal gate voltage (V int) at zero gate bias, which becomes more negative as the channel doping increases. The occurrence of negative V int is the unique feature of NCJL transistors, which is responsible for efficient channel depletion. The analysis showcases that negative V int in NCJL devices leads to lower off-current along with NC induced higher on-current than conventional JL devices. The results reported in this work provide insights into the functionality of NCJL devices and highlight the benefits of designing negative capacitance junctionless devices.

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Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications

Cited by 26 publications

References 25 publications

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate

Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors

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