Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks

Abstract

Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a) route packets using the minimal number of hops to reduce latency and preserve communication locality, (b) deliver good worst-case and averagecase throughput and (c) enable low-complexity (and hence, low latency) router implementation. In this paper, we focus on routing algorithms for an important class of interconnection networks: two dimensional (2D) mesh networks. Existing routing algorithms for mesh networks fail to satisfy one or more of design goals mentioned above. Variously, the routing algorithms suffer from poor worst case throughput (ROMM [13], DOR [24]), poor latency due to increased packet hops (VALIANT [32]) or increased latency due to hardware complexity (minimal-adaptive [7,31]). * This report is an expanded version of a previously published paper [18]. 1The major contribution of this paper is the design of an oblivious routing algorithm-O1TURN-with provable near-optimal worst-case throughput, good average-case throughput, low design complexity and minimal number of network hops for 2D-mesh networks, thus satisfying all the stated design goals. O1TURN offers optimal worst-case throughput when the network radix (k in a kxk network) is even. When the network radix is odd, O1TURN is within a 1/k 2 factor of optimal worst-case throughput. O1TURN achieves superior or comparable average-case throughput with global traffic as well as local traffic. For example, O1TURN achieves 18.8%, 0.7% and 13.6% higher average-case throughput than DOR, ROMM and VALIANT routing, respectively when averaged over one million random traffic patterns on an 8x8 network. Finally, we demonstrate that O1TURN is well suited for a partitioned router implementation that is of similar delay complexity as a simple dimension-ordered router. Our implementation incurs a marginal increase in switch arbitration delay that is completely hidden in pipelined routers as it is not on the clock-critical path.

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture

“…With comparison to the base NoC architecture, four-FIFO parallel buffer per incoming port achieves an optimal performance benefit. Also comparing with general virtual channel application [3] where at least 8 virtual channels per physical channel are required to get the nominal performance and resolve deadlock problem, the proposed NoC architecture with parallel buffers has its own benefit.…”

“…All these factors are taken into account when the design of an NoC architecture is considered. Regarding routing algorithms, many researchers have developed better performance routing algorithm using oblivious/deterministic or adaptive routing algorithms [1], [2], [3], [4], [5], [6]. In addition, the adoption of virtual channel (abbreviated to VC) has been prevailing because of its versatility.…”

Scalable, accurate multicore simulation in the 1000-core era

“…Static routing [7] is handled similarly. For O1TURN routing [8], illustrated in Figure 3b, the table at the start node (6) would contain two next-hop entries (one with next-hop node 3 and the other with next-hop node 7) weighted equally at 0.5, and the destination node (2) would have two entries (one arriving from node 1, and the other from node 5); the remaining tables do not differ from XY.…”

“…Current interconnects like buses, all-to-all point-topoint connections, and even rings clearly do not scale beyond a few cores. The relatively small scale of existing networkon-chip (NoC) interconnects has allowed plentiful on-chip bandwidth to make up for simple routing [4], but this will not last as scales grow from the 8 × 8 mesh of a 64-core chip to the 32 × 32 dimensions of a 1000-core: assuming all-to-all traffic and one flow per source/destination pair, a link in an 8 × 8 mesh with XY routing carries at most 128 flows, but in a 32 × 32 mesh, the worst link could be on the critical path of as many as 8,192 flows.…”

Static virtual channel allocation in oblivious routing

“…In o1turn [18], Seo et al show that simply balancing traffic between XY and YX routing can guarantee provable worst-case throughput. A weighted ordered toggle (WOT) algorithm that assumes 2 or more virtual channels (VCs) assigns XY and YX routes to source-destination pairs in a way that reduces the maximum network load for a given traffic pattern [9].…”