Static virtual channel allocation in oblivious routing

Shim, Keun Sup; Cho, Myong Hyon; Kinsy, Michel A.; Wen, Tina; Lis, Mieszko; Suh, G. Edward; Devadas, Srinivas

doi:10.1109/nocs.2009.5071443

Cited by 29 publications

(19 citation statements)

References 15 publications

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“…This directly supports dynamic VCA (all VCs are listed in the result with equal probabilities) as well as static set VCA [11] (the VC is a function of the flow ID). Most other VCA schemes used to avoid deadlock, such as that of O1TURN (where the XY and YX subroutes must be on different VCs), Valiant/ROMM (where each phase has a separate VC set), as well as various adaptive VCA schemes like the turn model [12], are easily implemented as a function of the current and next-hop flow IDs.…”

Section: A Network Modelmentioning

confidence: 74%

HORNET: A Cycle-Level Multicore Simulator

Ren

Lis

Cho

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on six separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 12×. Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, parameters driving power, and thermal effects. A highly parametrized

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Section: A Network Modelmentioning

confidence: 74%

HORNET: A Cycle-Level Multicore Simulator

Ren

Lis

Cho

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…This directly supports dynamic VCA (all VCs are listed in the result with equal probabilities) as well as static set VCA [12] (the VC is a function of on the flow ID). Most other VCA schemes used to avoid deadlock, such as that of O1TURN (where the XY and YX subroutes must be on different VCs), Valiant/ROMM (where each phase has a separate VC set), as well as various adaptive VCA schemes like the turn model [13], are easily implemented as a function of the current and next-hop flow IDs.…”

Section: A Network Modelmentioning

confidence: 76%

Scalable, accurate multicore simulation in the 1000-core era

Lis

Ren

Cho

et al. 2011

(Ieee Ispass) Ieee International Symposium on Performance Analysis of Systems and Software

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Abstract-We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued wormhole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical cores on a single die, speedups can exceed a factor of over 5, and when run on a two-die 12-core system with 2-way hyperthreading, speedups exceed 11×.Most hardware parameters are configurable, including memory hierarchy, interconnect geometry, bandwidth, crossbar dimensions, and parameters driving power and thermal effects. A highly parametrized table-based NoC design allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing. HORNET can run in network-only mode using synthetic traffic or traces, directly emulate a MIPS-based multicore, or function as the memory subsystem for native applications executed under the Pin instrumentation tool.HORNET is freely available under the open-source MIT license at http://csg.csail.mit.edu/hornet/.

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“…Shim et al [19] propose a similar approach that statically binds flows to specific VCs at design time. Both approaches prevent blocked flows from acquiring more than a single VC at each input buffer, but neither limits the amount of buffer space occupied by that VC.…”

Section: Related Workmentioning

confidence: 99%

Adaptive Backpressure: Efficient buffer management for on-chip networks

Becker

Jiang

Michelogiannakis

et al. 2012

2012 IEEE 30th International Conference on Computer Design (ICCD)

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Abstract-This paper introduces Adaptive Backpressure, a novel scheme that improves the utilization of dynamically managed router input buffers by continuously adjusting the stiffness of the flow control feedback loop in response to observed traffic conditions. Through a simple extension to the router's flow control mechanism, the proposed scheme heuristically limits the number of credits available to individual virtual channels based on estimated downstream congestion, aiming to minimize the amount of buffer space that is occupied unproductively. This leads to more efficient distribution of buffer space and improves isolation between multiple concurrently executing workloads with differing performance characteristics.Experimental results for a 64-node mesh network show that Adaptive Backpressure improves network stability, leading to an average 2.6× increase in throughput under heavy load across traffic patterns. In the presence of background traffic, the proposed scheme reduces zero-load latency by an average of 31 %. Finally, it mitigates the performance degradation encountered when latency-and throughput-optimized execution cores contend for network resources in a heterogeneous chip multi-processor; across a set of PARSEC benchmarks, we observe an average reduction in execution time of 34 %.

show abstract

Static virtual channel allocation in oblivious routing

Cited by 29 publications

References 15 publications

HORNET: A Cycle-Level Multicore Simulator

HORNET: A Cycle-Level Multicore Simulator

Scalable, accurate multicore simulation in the 1000-core era

Adaptive Backpressure: Efficient buffer management for on-chip networks

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