Near-optimal critical sink routing tree constructions

Abstract

We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "global slack removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67 %) over minimum Steiner routings in terms of delays to identified critical sinks. ERT's also serve as generic high-performance routing trees when no critical sink is specified: for 8-sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the minimum Steiner routing. These approaches provide simple, basic advances over existing performance-driven routing tree constructions. Our results are complemented by a detailed analysis of the accuracy andwelity of the Elmore delay approximation; we also exactly assess the suboptimality of our heuristic tree constructions. In achieving the latter result, we develop a new characterization of Elmore-optimal routing trees, as well as a decomposition theorem for optimal Steiner trees, which are of independent interest. I. INTRODUCTION UE to the scaling of VLSI technology, interconnection D delay has become a dominant concern in the design of complex, high-performance circuits [ 131, [34]. Performancedriven layout design has thus become an active area of research over the past several years. In this paper, we develop a new critical-sink problem formulation and new solutions for performance-driven routing tree design. For a given signal net, the typical goal of performancedriven routing is to minimize average or maximum sourcesink delay. Much early work implicitly equates optimal routing with minimum-cost Steiner routing. For example, [ 141 used static timing analysis to yield net priorities, so that Manuscript

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

“…cannot lead to an optimal solution [8]. An important contribution of our work is recognizing that the valid Steiner points for connecting to edge…”

“…The objective of previous timing-driven (TD) routers have been varied, ranging from minimizing the average source-tosink delay to minimizing the maximum source-to-sink delay over all sinks [8,9] to minimizing interconnect length subject to satisfying all timing specifications [6]. The latter is the exact TD problem that needs to be solved, although possibly with added optimization criteria such a minimizing the number of vias and routing layers.…”

“…For each benchmark circuit, we generated 10 different random ECOs, and the results given for each circuit are averaged over these 10 runs. We compared TIDE to the timingdriven versions of two prior incremental routing techniques Std [1] and R&R [2] implemented by us overlaid on a TD routing algorithm SERT/SOAR composed of elements of two well-known prior TD routing algorithms, SERT-C [8] and SOAR [9]. We term these incremental TD algorithms TD-Std and TD-R&R.…”

Timing-Driven Interconnect Synthesis

“…Thus, formulations which optimized delays with respect to a set of critical sinks proved more effective than ones that optimized delays in individual nets while ignoring the critical sinks [62]. The near-optimality of minimum-delay routing heuristics was also quantified empirically, showing e.g., that certain simple heuristics achieved almost optimal critical sink delays [9,10,62,69]. Other advances in timing-driven interconnect synthesis for improving circuit performance included various approaches to wiresizing, non-Hanan routing, non-tree topologies, and arborescence trees.…”

“…For example, an early sequence of papers by Boese, Kahng, and Robins [7,8,9,10] proposed new classes of delay objectives, along with improved-performance routing algorithms that directly optimized, e.g., the Elmore delay. These works also established the fidelity of Elmore-based constructions relative to accurate delay simulators (e.g., SPICE) [62].…”