Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Dutt, Shantanu; Arslan, Hasan

doi:10.1109/date.2006.244117

Cited by 4 publications

(2 citation statements)

References 11 publications

(21 reference statements)

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“…Research on ECO and incremental algorithms has focused on traditional costs such as wire-length, timing closure, and the number of changed nets (see for example [Chen et al 2007;Dutt and Arslan 2006;Roy and Markov 2007]); however, they are too general to be used to distinguish between timing-feasible solutions with very similar power, but very different implementation cost.…”

Section: Eco Costmentioning

confidence: 99%

ECO cost measurement and incremental gate sizing for late process changes

Lee

Gupta

2013

ACM Trans. Des. Autom. Electron. Syst.

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Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an Engineering Change Order (ECO) to correct these problems. We present a framework to perform incremental gate sizing for process changes late in the design cycle, and a method to create initial designs that are robust to late process changes. This includes a method to measure and estimate ECO cost, and to transform these costs into linear programming optimization problems. In the case of ECOs, on average, the method reduces ECO costs by an average of 89% in changed area compared to a leading commercial tool. Furthermore, the robust initial designs are, on average, 55% less likely to need redesign in the future.

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Section: Eco Costmentioning

confidence: 99%

ECO cost measurement and incremental gate sizing for late process changes

Lee

Gupta

2013

ACM Trans. Des. Autom. Electron. Syst.

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“…Commonly used path search algorithms include basic Dijkstra and the A* algorithm [18]. Dutt et al [15] present an algorithm to perform incremental routing using Dijkstra algorithm to connect nodes to an existing tree in a restricted interval that satisfies the timing constraint. Hur et al [16] present a method based on a multi-graph model for performance driven routing of two pin nets with wire sizing.…”

Section: B Algorithms For Steiner Tree Constructionmentioning

confidence: 99%

Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff

Hentschke

Narasimhan

Johann

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.

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