Navigating registers in placement for clock network minimization

Lü, Yongqiang; Sze, Cliff; Hong, Xianlong; Zhou, Qiang; Cai, Yici; Huang, Liang; Hu, Jiang

doi:10.1145/1065579.1065628

Cited by 35 publications

(17 citation statements)

References 17 publications

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“…To address the apparent conflict between clock-net optimization and traditional placement objectives, some researchers proposed techniques and algorithms for better register placement without intrusive interference in traditional placement objectives. Lu [15] proposed several techniques including Manhattan ring-based register guidance, center-of-gravity constraints for registers, pseudo-pins and register-cluster contraction. Cheon [4] proposed power-aware placement that performs both activity-based register clustering and activitybased net weighting to simultaneously reduce the clock and signal net-switching power.…”

Section: Prior Workmentioning

confidence: 99%

“…Manhattan-ring guidance methods commit registers to certain guidance locations and try to pull the registers close to the nearest such locations during placement [15]. However, such methods do poorly in the presence of numerous obstacles, e.g., macro-blocks, or when register locations found by the global placer are not uniformly distributed.…”

Section: Prior Workmentioning

confidence: 99%

“…However, prior publications used the benchmarks without macro blocks or ignored macro blocks present in the benchmarks [30]. (4) Reference placement tools used for comparison are often outdated [15] or self-implemented [30]. Such comparisons risk not being representative of state-ofthe-art EDA tools.…”

Section: Empirical Validationmentioning

confidence: 99%

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Obstacle-aware clock-tree shaping during placement

Lee

Markov

2011

Proceedings of the 2011 International Symposium on Physical Design

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Traditional IC design flows optimize clock networks before signal-net routing and are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-network synthesis.In this work, we integrate clock network synthesis within global placement by optimizing register locations. We propose the following techniques: (1) obstacle-aware virtual clock-tree synthesis; (2) arboreal clock-net contraction force with virtual-node insertion, which can handle multiple clock domains and gated clocks; (3) an obstacle-avoidance force. Our work is validated on large-size benchmarks with numerous macro blocks. Experimental results show that our software implementation, called Lopper, prunes clock-tree branches to reduce their length by 30.0%∼36.6% and average total dynamic power consumption by 6.8%∼11.6% versus conventional approaches.

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Section: Prior Workmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

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Obstacle-aware clock-tree shaping during placement

Lee

Markov

2011

Proceedings of the 2011 International Symposium on Physical Design

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“…However, overemphasizing the placement of clock sinks may elongate signal nets and undermine their timing. To this end, Lu [20] proposed Manhattan ring-based register guidance in global placement, center-of-gravity constraints for registers, pseudo-pins and register-cluster contraction. Cheon [5] proposed power-aware placement that performs both activity-based register clustering and activity-based net weighting to simultaneously reduce the clock and signal net-switching power.…”

Section: Interactions Between Placement and Clock-network Synthesismentioning

confidence: 99%

Algorithmic tuning of clock trees and derived non-tree structures

Lee¹

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.I. INTRODUCTION Clock-network synthesis significantly impacts the performance, area and power dissipation of an integrated circuit, and this impact is aggravated when architectural-level pipelining increases the number of clocked elements [35]. Being responsible for 30-50% of chip power [9], clock networks require careful optimization. Such optimization may require SPICEaccurate timing analysis, otherwise it is difficult to account for the explosion of technology parameters that characterize each advanced technology node. Unfortunately, runtime overhead limits such analysis to only several invocations during optimization. Recent research reviewed in this paper developed comprehensive SPICE-accurate clock-network optimizations subject to capacitance and slew constraints, and cognizant of runtime limitations. The ISPD 2009 and 2010 Clock-Network Synthesis contests organized by IBM Research and Intel Research evaluated these techniques on industry benchmarks. The second contest increased the realism in modeling and evaluation of clock networks, adding the impact of variations and using local rather than global clock skew -a more meaningful parameter for large circuits [10].The growing impact of process, voltage and temperature (PVT) variation complicates the design of reliable clock networks [26], as nominal-parameter optimizations (single corner, no variation) do not ensure high yield. Robustness to variations requires increased power and careful trade-offs. Mesh/grid structures exhibit greater robustness but consume much more power and complicate clock gating. This paper surveys recent clock-network topologies that offer the path-redundancy of meshes, but retain the advantages of clock trees.Clock networks can also be improved by careful positioning of latches and flip-flops. Leaf-level register clustering [3] after global placement can help sharing inverters between flip-flops and reduce clock-network capacitance. In this paper, we review a recent, more general optimization [17] that differentiates sequential elements during global placement and optimizes total dynamic power of signal nets and the clock network.

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“…Energy recovery is also a feasible approach adopted in [8]. Lu et al [6] and Lou et al [10] focus on minimizing clock networks through replacing non-timingcritical cells with their high V t counter parts.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction

Chang

Hwang

2012

IIS

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Power optimization has always been an important issue for modern IC design. In this paper, we present a power optimization technique for clock tree by applying multi-bit flip-flops and reducing total wire length. Through merging flip-flops into MBFFs, we effectively reduce power consumption caused by clock buffers. Moreover, by judiciously merging and placing the MBFFs, the total wire length is also significantly reduced. The combined effect of both techniques leads to a strong reduction in total power consumption of the clock network.

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Navigating registers in placement for clock network minimization

Cited by 35 publications

References 17 publications

Obstacle-aware clock-tree shaping during placement

Obstacle-aware clock-tree shaping during placement

Algorithmic tuning of clock trees and derived non-tree structures

Synthesis of Multi-Bit Flip-Flops for Clock Power Reduction

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