Algorithmic tuning of clock trees and derived non-tree structures

Abstract

Abstract-This mini-tutorial covers recent research on clocknetwork tuning. It starts with SPICE-accurate optimizations used in winning entries at the ISPD 2009 and 2010 clock-network synthesis contests. After comparing clock trees to meshes, it outlines a recent redundant clock-network topology that retains most advantages of clock trees, but improves robustness to PVT variations. It also shows how to incorporate clock-network synthesis into global placement to reduce dynamic power and insertion delay.I. INTRODUCTION Clock-network synthesis significantly impacts the performance, area and power dissipation of an integrated circuit, and this impact is aggravated when architectural-level pipelining increases the number of clocked elements [35]. Being responsible for 30-50% of chip power [9], clock networks require careful optimization. Such optimization may require SPICEaccurate timing analysis, otherwise it is difficult to account for the explosion of technology parameters that characterize each advanced technology node. Unfortunately, runtime overhead limits such analysis to only several invocations during optimization. Recent research reviewed in this paper developed comprehensive SPICE-accurate clock-network optimizations subject to capacitance and slew constraints, and cognizant of runtime limitations. The ISPD 2009 and 2010 Clock-Network Synthesis contests organized by IBM Research and Intel Research evaluated these techniques on industry benchmarks. The second contest increased the realism in modeling and evaluation of clock networks, adding the impact of variations and using local rather than global clock skew -a more meaningful parameter for large circuits [10].The growing impact of process, voltage and temperature (PVT) variation complicates the design of reliable clock networks [26], as nominal-parameter optimizations (single corner, no variation) do not ensure high yield. Robustness to variations requires increased power and careful trade-offs. Mesh/grid structures exhibit greater robustness but consume much more power and complicate clock gating. This paper surveys recent clock-network topologies that offer the path-redundancy of meshes, but retain the advantages of clock trees.Clock networks can also be improved by careful positioning of latches and flip-flops. Leaf-level register clustering [3] after global placement can help sharing inverters between flip-flops and reduce clock-network capacitance. In this paper, we review a recent, more general optimization [17] that differentiates sequential elements during global placement and optimizes total dynamic power of signal nets and the clock network.

Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

“…In this experiment, we achieved 28.89% better global skew with PA compare to the CTS. Clock re-convergence pessimism (CRP) is a difference in delay along the common part of the launching and capturing clock paths which models the impact of variation on skew that causes inaccuracy in timing [53] while clock re-convergence pessimism removal (CRPR) is an automated correction of this inaccuracy in timing calculation which is available in most of the design tools. Higher CRPR value in a timing path directly indicates lower OCV induced jitter effects on the clock distribution network of the path.…”

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

“…The basics of Clock Tree Synthesis (CTS) is to develop the interconnect that connects the system clock into all the cells in the chip that uses the clock (Markov and Lee, 2011) For CTS, your major concerns are:…”

“…Next buffering and wire sizing is easily determined by topdown approach. It will be useful for modeling the constraints over the simulation, easy to handle the timing problems (Markov and Lee, 2011). The optimal guarantees the sub tree and propagate the solution towards the root tree Node, but do not guarantee the local adjustment.…”

Synthesis and exploration of clock spines

“…In contrast, the clock tree with links provides a reasonable solution which compromises clock resource with clock skew variation by adding cross links to internal nodes on the clock tree (e.g. [10][11][12][13]). Since the determination of the placement locations on the clock tree at which links are inserted directly affects the degree of clock skew variation, the main issue of the algorithms synthesising clock tree with links is to find a minimal number of internal locations on the clock tree at which the links are inserted to meet the constraint of clock skew variation (e.g.…”

“…Since the determination of the placement locations on the clock tree at which links are inserted directly affects the degree of clock skew variation, the main issue of the algorithms synthesising clock tree with links is to find a minimal number of internal locations on the clock tree at which the links are inserted to meet the constraint of clock skew variation (e.g. [11][12][13]). In addition to the clock tree with links, clock spine is another alternative to the clock tree with links, but the structure is totally different.…”