Native mode functional self-test generation for Systems-on-Chip

Jayaraman, K. S.; Vedula, V.M.; Abraham, Jacob A.

doi:10.1109/isqed.2002.996752

Cited by 22 publications

(17 citation statements)

References 11 publications

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“…Recently, SBST techniques have been extended to peripheral testing [5] [10][11][12][13][14]. Jayaraman et al [5] proposed a functional software-based test approach and applied it to an 8251-compatible USART; the proposed methodology, however, shows rather low stuck-at fault coverage (67.89%).…”

Section: A Backgroundmentioning

confidence: 99%

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A software-based self-test methodology for system peripherals

Grosso

Perez

Ravotto

et al. 2010

2010 15th IEEE European Test Symposium

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Software-based self-test strategies have been mainly proposed to tackle microprocessor testing issues, but may also be applied to peripheral testing. However, testing highly embedded peripherals (e.g., DMA or Interrupt controllers) is a challenging task, since their observability and controllability are even more reduced compared to microprocessors and to peripherals devoted to I/O communication (e.g., serial or parallel ports). In this paper we describe an approach to develop functional tests for system peripherals embedded in SoCs that can be used for both design validation and testing. The presented methodology requires two correlated phases: module configuration and module operation. The first one prepares the peripheral on the different operation modes, whereas, the second one is in charge of exciting the whole device and observing its behavior. A methodology for generating suitable test programs is proposed, and preliminary experimental results demonstrating the method effectiveness for an embedded DMA controller are finally reported.

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Section: A Backgroundmentioning

confidence: 99%

“…However, new techniques have been developed in the last years to deal with the most recent processor architectures; moreover, some techniques aim at supporting the test program generation starting from highlevel, or purely functional descriptions [5]; in other cases, a pre-synthesis RT-level description is required.…”

Section: Introductionmentioning

confidence: 99%

A software-based self-test methodology for system peripherals

Grosso

Perez

Ravotto

et al. 2010

2010 15th IEEE European Test Symposium

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show abstract

“…Differently from the manual method, in [11] a pseudo-exhaustive approach to generate functional programs for peripheral testing was presented. The proposed method generates a functional program for each possible operation mode of the peripheral core in order to generate control sequences which would place the peripheral in all possible functional modes.…”

Section: Figure 3 Test Set Generation Schemementioning

confidence: 99%

“…The pseudo-exhaustive approach [11] gives rise to a large number of functional programs, since one has to be written for every operation mode; this implies a large application time and a considerable memory occupation.…”

Section: Figure 3 Test Set Generation Schemementioning

confidence: 99%

Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores

Bolzani

Sánchez

Schillaci

et al. 2007

Proceedings of the 9th Annual Conference on Genetic and Evolutionary Computation

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Test of peripheral modules has not been deeply investigated by the research community. When embedded in a system on chip, however, peripherals pose accessibility problems that may make traditional test approaches ineffective. In this paper an evolutionary methodology, based upon coverage metrics at highlevel, is described to automatically generate test sets for peripheral modules in a SoC. A general-purpose evolutionary tool, able to cultivate composite individuals, has been developed and is used for the test set generation. This tool is described and its basic concepts explained. The method compares favorably with results obtained by hand.

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“…This gives an opportunity to use the functionality of such particular core also for SoC testing purposes. As a result, many researchers have recently proposed ideas for testing SoC components where an embedded processor controls the test data traffic [7], [8], [9] between the test controller and the SoC. However, there is a clear lack of recent academic research on testing beyond the SoCs.…”

Section: Introductionmentioning

confidence: 99%

SoC and Board Modeling for Processor-Centric Board Testing

Tsertov

Ubar

Jutman³

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that the restricted capabilities of BS with respect of such modern challenges as dynamic (timing-accurate), at-speed and high-speed testing as well as in-system programming create considerable troubles for test engineers in production environments. In this paper, we point out particular challenges in testing the system's infrastructure beyond the SoCs as well as propose a general modeling methodology for test automation for microprocessor SoC-based system boards. The new so-called "Lego-style" test automation methodology forms a complimentary solution to traditional boundary scan. Together, they provide extended fault coverage that targets shorts, opens, stuck-at faults as well as dynamic faults (e.g. delays and transition faults). The "Legostyle" model allows reducing the labour effort drastically once the library of model components is created.

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Native mode functional self-test generation for Systems-on-Chip

Cited by 22 publications

References 11 publications

A software-based self-test methodology for system peripherals

A software-based self-test methodology for system peripherals

Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores

SoC and Board Modeling for Processor-Centric Board Testing

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