Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

Musalgaonkar, Gaurav; Sahay, Shubham; Saxena, Raghvendra Sahai; Kumar, M. Jagadesh

doi:10.1109/ted.2019.2933756

Cited by 55 publications

(25 citation statements)

References 28 publications

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Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

“…Based on the previous works of nanotube MOSFETs [27][28][29], the suggested fabrication process flow for CIGAA is shown in Figure 3. The CIGAA can be realized using the process flow suggested in [28] with some major changes. The first steps of the fabrication process is to form a cylindrical-shaped outer silicon layer with a sidewall using electron beam lithography (EBL) and sidewall deposition (Figure 3a-e), as suggested in [28].…”

Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

“…The CIGAA can be realized using the process flow suggested in [28] with some major changes. The first steps of the fabrication process is to form a cylindrical-shaped outer silicon layer with a sidewall using electron beam lithography (EBL) and sidewall deposition (Figure 3a-e), as suggested in [28]. Then, the source side spacer is formed using low-pressure chemical vapor deposition (LPCVD), and the following step ( Figure 3f) is to remove unnecessary spacer material that is covered on the sidewall and cylindrical-shaped outer silicon layer using lithography and etching.…”

Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

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A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Zhang

Han

2020

Micromachines

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Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

Section: Suggested Fabrication Process Flow For Cigaamentioning

confidence: 99%

See 1 more Smart Citation

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Zhang

Han

2020

Micromachines

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“…All simulation results in this study were obtained using the nonlocal BTBT model, Shockley-Read-Hall recombination model, bandgap narrowing model, and doping dependence mobility model in Synopsys Sentaurus TCAD. The parameters used to calibrate the nonlocal BTBT model were A = 4 × 10 14 cm −3 s −1 , and B = 19 × 10 6 V/cm for silicon and A = 1.46 × 10 17 cm −3 s −1 , and B = 3.59 × 10 6 V/cm for germanium [1].…”

Section: Device Structures and Simulation Methodsmentioning

confidence: 99%

“…However, in conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), subthreshold swing (SS) is limited to 60 mV/decade (SS = (kT/q) × ln10) at room temperature. This limitation prevents the supply voltage from being reduced at the same pace as the scaling of the physical dimensions of semiconductor devices [1][2][3][4][5]. To overcome this problem, researchers have been studying devices with a steep SS.…”

Section: Introductionmentioning

confidence: 99%

A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

et al. 2020

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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

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Performance analysis of electrostatic plasma-based dopingless nanotube TFET

Gupta

Raman

2020

Appl. Phys. A

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Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

Cited by 55 publications

References 28 publications

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Performance analysis of electrostatic plasma-based dopingless nanotube TFET

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