A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Abstract

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

Analytical investigation of a triple surrounding gate germanium source metal–oxide–semiconductor field‐effect transistor with step graded channel for biosensing applications

“…TSG‐GSM‐SGCB detection principle is based on this fundamental concept and is shown in Figure 2A. Fabrication of the biosensor starts with some elementary fabrication steps [40–42] like wafer preparation and cleaning, silicon epitaxial growth, sacrificial layer deposition and deposition of n‐type silicon body with uniform step doping over heavily doped drain (etched a number of times) for forming a vertical pillar like annular region [43]. The remaining fabrication steps are shown in the form of diagrammatic flowchart in Figure 2B.…”

Gate-all-around junctionless FET based label-free dielectric/charge modulation detection of SARS-CoV-2 virus

“…The GAA-JLFET structure can be realized using the process suggested in. 16,17 Further, to realize cavity in the device tunnel-etching process can be used. 18 In tunnel etching process a SiGe layer is grown on Si substrate and on this layer gate metal contact is grown.…”

Gate-All-Around Nanowire TFET with Heterojunction and Core Insulator: Design and Analysis

“…To overcome these issues various researchers, have proposed devices for example impact ionization MOS devices, finFET, and Tunnel Field Effect Transistors (TFETs). 6 Out of these, the most viable device to replace MOSFETs turned out to be TFETs since TFET outperforms in terms of subthreshold swing (which is below 60 mV dec −1 ), low off-state current I OFF and low SCEs.…”

“…Although TFET offers certain advantages over MOSFET, its lower ON-current (I ON ) capability has to be addressed. A variety of methods, comprising the usage of high-k dielectric, 6,7 band gap engineering, 8,9 the insertion of heavily doped layers at the source channel interface, 10 heterojunction structures, [11][12][13][14] and others, have been proposed by certain researchers to improve I ON of TFET. According to IRDS 2022 report summary, "GAA is expected to become a mainstream device in 2025 with the early introduction in 2022."…”

“…Moreover, the SS and leakage current may also be further improved. 6,12,[17][18][19][20] Furthermore, Germanium material integrates well on Si substrates, has a narrow effective bandgap (E g ), is relatively inexpensive, and has great symmetry. Low E g generates a high BTBT current, which increases the I ON /I OFF ratio.…”