Nanosilicon for single-electron devices

Mizuta, Hiroshi; Furuta, Yoshikazu; Kamiya, Toshio; Tan, Yong Ren; Durrani, Z. A. K.; Amakawa, Shuhei; Nakazato, Kazuhiko; Ahmed, H.

doi:10.1016/j.cap.2003.10.005

Cited by 3 publications

(4 citation statements)

References 19 publications

(21 reference statements)

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“…The V GD sweep with V SD = −0.1V roughly mirrored the sweep with V SD = 0.1V in Figure 5, thus suggesting weak Coulomb oscillations. Mizuta et al [13] had similar results using material properties. Imperfections may have led to unusually small islands, with much lower island capacitance C Σ , allowing higher operating T .…”

Section: Samplesupporting

confidence: 63%

“…Kamiya et al [12] enhanced grain boundary (GB) potential barriers by oxidation and annealing. Mizuta et al [13] made SETs with poly/nanocrystalline material, and created a point-contact transistor SET. Uchida et al [2,14] made islands of only a few nm by reducing the Si nanowire thickness by chemical treatment, leaving the island with undulated areas that functioned as tunneling barriers.…”

Section: Prior Workmentioning

confidence: 99%

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Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

Mazor

Bushnell

Mulligan

et al. 2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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We improved Smith and Ahmed's nanowire singleelectron transistor (SET) to change its operating temperature from 4.2 o K to room temperature. We made more than 1000 nanotechnology SETs on the fabrication line. We characterized their faults, the yield, the dependence of faults on the process, and the correlation between channel width and faults. We improved the SET process recipe. SETs are made on silicon-on-insulator (SOI) wafers using an E-beam lithography machine (the Raith 150) to create two L-shaped trenches in the Si; these are etched through to the SiO 2 insulating layer using reactive ion etching (RIE). After process improvements, our yield was 24.3% working SETs, of which 79.4% had significant Coulomb oscillations at room temperature. Also, 20.6% of the SETs had stuck-open transistors, 50.7% had resistive bridges, and 4.4% had gross defects, from severe fabrication line contamination.

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Section: Samplesupporting

confidence: 63%

Section: Prior Workmentioning

confidence: 99%

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

Mazor

Bushnell

Mulligan

et al. 2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

View full text Add to dashboard Cite

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“…Silicon (Si) nano/microstructures fabricated by nano/micromachining have attracted much interest in applications of three-dimensional transistors, nanoelectrics, energy harvesting materials, batteries, highly sensitive sensors, , and metamaterials . In particular, Si nano/micromachining through metal-assisted chemical etching (MACE) is regarded as an influential method due to its simplicity, low cost, high throughput, high crystalline quality, and applicability under ambient conditions. − In general, MACE for Si nano/micromachining is carried out in a mixture solution of hydrogen fluoride (HF) and hydrogen peroxide (H 2 O 2 ); holes are produced through the reduction process of H 2 O 2 by a catalytic reaction with the noble metal contacting Si .…”

Section: Introductionmentioning

confidence: 99%

Optimized Hole Injection, Diffusion, and Consumption for Efficient Metal-Assisted Chemical Etching Depending on the Silicon Doping Type and Metal Catalyst Area

Jang

2021

J. Phys. Chem. C

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Even though metal-assisted chemical etching (MACE) has been widely used for silicon (Si) nano/micromachining due to its low cost and high applicability, it is still difficult to fabricate elaborate Si nano/microstructures for high-value applications. In particular, further studies about effective factors in the MACE process with systematic approaches are highly required to obtain explicitly controlled MACE products. In this study, how the Si doping type and gold (Au) catalyst area influence MACE products in terms of the hole behavior during MACE is investigated. The type-dependent etching rate of MACE, amount of reaction products, and lateral etching/porosity of the MACE product are characterized with hole injection, diffusion, and consumption scenarios, respectively. Moreover, it is demonstrated that the dependence of the etching rate of MACE and stability/porosity of the MACE product on the Au catalyst area can be understood from the point of view of hole injection per interfacial contact plane area of the Au catalysts. As a result, elaborately controlled Si nano/microstructures can be obtained through an effective and accurate MACE process due to the optimized hole behavior. These findings could increase the accessibility and commercial availability of MACE products in many fields.

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“…During the past few years, optoelectronic and nanoelectronic devices, such as light emitters [1][2][3], optical modulators [4], single electron devices [5,6] and NonVolatile Memory devices (NVM) [7][8][9] have exploited the physical properties of silicon nanocrystals (Si-NCs) embedded in a dielectric matrix. Memory devices consisting of a metal-oxide-semiconductor field-effect transistor (MOSFET) with nanocrystals are promising candidates for high storage density low power memory applications.…”

Section: Introductionmentioning

confidence: 99%

Controlled fabrication of Si nanocrystals embedded in thin SiON layers by PPECVD followed by oxidizing annealing

et al. 2010

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The controlled fabrication of Si nanocrystals embedded in thin silicon oxynitride films (<15 nm) on top of a silicon substrate has been realized by PPECVD with N(2)O-SiH(4) precursors. The effect of inert and oxidizing annealing processes on the Si nanocrystal spatial and size distributions is studied by coupling ellipsometry measurements and cross-sectional transmission electron microscopy observations. This study gives an interesting insight into the physics underlying the Si nanocrystal nucleation, growth and oxidation mechanisms. In particular, it evidences the presence in the as-deposited films of a high density of small amorphous Si particles that crystallize after high temperature thermal annealing. Annealing under oxidizing conditions is shown to be a powerful way to create tunnel oxides of good quality and controlled thickness needed to design future memory devices.

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Nanosilicon for single-electron devices

Cited by 3 publications

References 19 publications

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors

Optimized Hole Injection, Diffusion, and Consumption for Efficient Metal-Assisted Chemical Etching Depending on the Silicon Doping Type and Metal Catalyst Area

Controlled fabrication of Si nanocrystals embedded in thin SiON layers by PPECVD followed by oxidizing annealing

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