1999
DOI: 10.1063/1.123059
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Nanometer patterning of epitaxial CoSi2/Si(100) for ultrashort channel Schottky barrier metal–oxide–semiconductor field effect transistors

Abstract: A nanometer patterning method, based on local oxidation of silicide layers, was used to pattern epitaxial CoSi2 layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi2 layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky source/drain metal–oxide–semiconductor field effect transistor with epitaxial CoSi2 on p-Si(100) was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.

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Cited by 37 publications
(23 citation statements)
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“…While earlier devices exhibited low drive currents [6,7], recent experimental research has focused on either device fabrication or operation at low temperatures [8][9][10]. Other researchers have successfully used SiGe as the source/drain [11], or concentrated on silicon-on-insulator (SOI) devices [12,13].…”
Section: Introductionmentioning
confidence: 99%
“…While earlier devices exhibited low drive currents [6,7], recent experimental research has focused on either device fabrication or operation at low temperatures [8][9][10]. Other researchers have successfully used SiGe as the source/drain [11], or concentrated on silicon-on-insulator (SOI) devices [12,13].…”
Section: Introductionmentioning
confidence: 99%
“…Feature sizes of useful components in microelectromechanical systems ͑MEMS͒ 2,3 and electronic devices 3 are becoming smaller, reaching nanometer ranges. [3][4][5] Their large surface-to-volume ratios make the components more susceptible to environmental effects. For example, a MEMS-based mechanical testing 6 has shown the existence of fatigue ͑i.e., crack growth under repeated subcritical loading͒ at a submicron-sized crack in Si, although there is no fatigue in bulk Si.…”
Section: Introductionmentioning
confidence: 99%
“…Schottky-barrier MOSFET (SB-MOSFET) offers an alternative device technology to minimize parasitic S/D resistances and eliminate the need for ultra-shallow junctions [1][2][3][4][5][6][7][8][9]. The characteristics of nano scale SB-MOSFETs based on ballistic simulation and constant effective mass approximation have been reported [10,11].…”
Section: Introductionmentioning
confidence: 99%