NAND overview: from memory to systems

Micheloni, Rino; Marelli, Alessia; Commodaro, S.

doi:10.1007/978-90-481-9431-5_2

Cited by 17 publications

(14 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In MLC NAND Flash, each cell stores 2-bit information by setting cell V th into 4 non-overlapping voltage windows. As the conventional definition, one bit in a cell belongs to the least significant bit (LSB) page and the other bit belongs to the most significant bit (MSB) page [12]. Figure 1 illustrates cell voltage distributions during basic operations.…”

Section: Mlc Nand Flash Basicmentioning

confidence: 99%

LSB page refresh based retention error recovery scheme for MLC NAND Flash

Liu

Pan

et al. 2016

Sci. China Inf. Sci.

View full text Add to dashboard Cite

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

show abstract

Section: Mlc Nand Flash Basicmentioning

confidence: 99%

LSB page refresh based retention error recovery scheme for MLC NAND Flash

Liu

Pan

et al. 2016

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…The typical organization of NAND memories can be represented by a hierarchical structure comprised of the following different elements [3][4][5] NOR memories are able to read and write single bytes, NAND memories must access on groups of bytes called pages and they erase groups of pages called blocks. Therefore, NOR memories perform much faster access to single data if compared with NAND memories.…”

Section: Nand Flash Memorymentioning

confidence: 99%

“…The typical organization of NAND memories can be represented by a hierarchical structure comprised of the following different elements [3][4][5]:…”

Section: Nand Flash Memorymentioning

confidence: 99%

“…The software managing the flash memories is called Flash Translation Layer (FTL). Its main functionalities are [4][5][6][7][8]:…”

Section: Nand Flash Memorymentioning

confidence: 99%

“…Recently, many methods and tools for the exploration of the NAND flash memory architecture have been proposed and several SSD simulators have been developed [4][5][6][7][8][9][10][11][12][13].…”

mentioning

confidence: 99%

See 2 more Smart Citations

SystemC/TLM Controller for Efficient NAND Flash Management in Electronic Musical Instruments

Conti

Caldari²,

Gianfelici

et al. 2018

Electronics

View full text Add to dashboard Cite

The design of an efficient memory subsystem is a fundamentally challenging task in the design of electronic equipment. The storage hierarchy chosen for a particular design has a significant impact on the overall performance and cost. Flash memory often contains the boot code, operating system kernel, device drivers, middleware, and other application-specific software that can result in megabytes of non-volatile stored data. To maximize the performance, data are moved from non-volatile memory to faster SDRAM (synchronous dynamic random-access memory). Non-volatile memory technologies reach a performance level close to that of dynamic RAMs with the additional benefit of persistent data storage. When cost is critical, an approach where the data are managed directly from non-volatile memory can be used. In this case the non-volatile memory subsystem is constantly accessed to retrieve data. The deep understanding of the system architecture is critical to identify any factor that affects memory performance and the resulting system performance; particularly in specific applications with stricter requests like streaming audio when more than one hundred data streams must be handled in a real-time environment and sound must be generated with a total latency of a few milliseconds. This article reports the development of the system-level model of a controller in a SystemC simulation environment capable of optimizing the use of NAND type flash memories for storage and playback of audio samples in real-time music applications, with the aim of reducing the quantity of the system SDRAM memory, thus lowering the cost of the final product, while still providing the most high-fidelity sound experience.

show abstract

A Proposed Framework: Enhanced Automated Duplication Algorithm for Flash Application

Rostam

Abdullah

2019

Intelligent and Interactive Computing

View full text Add to dashboard Cite

NAND overview: from memory to systems

Cited by 17 publications

References 10 publications

LSB page refresh based retention error recovery scheme for MLC NAND Flash

LSB page refresh based retention error recovery scheme for MLC NAND Flash

SystemC/TLM Controller for Efficient NAND Flash Management in Electronic Musical Instruments

A Proposed Framework: Enhanced Automated Duplication Algorithm for Flash Application

Contact Info

Product

Resources

About