N-MOSFETs Formed on Solid Phase Epitaxially Grown GeSn Film with Passivation by Oxygen Plasma Featuring High Mobility

Abstract

Solid phase epitaxially grown GeSn was employed as the platform to assess the eligibility of direct O2 plasma treatment on GeSn surface for passivation of GeSn N-MOSFETs. It has been confirmed that O2 plasma treatment forms a GeSnO(x) film on the surface and the GeSnO(x) topped by in situ Al2O3 constitutes the gate stack of GeSn MOS devices. The capability of the surface passivation was evidenced by the low interface trap density (D(it)) of 1.62 × 10(11) cm(-2) eV(-1), which is primarily due to the formation of Ge-O and Sn-O bonds at the surface by high density/reactivity oxygen radicals that effectively suppress dangling bonds and decrease gap states. The good D(it) not only makes tiny frequency dispersion in the characterization of GeSn MOS capacitors, but results in GeSn N-MOSFETs with outstanding peak electron mobility as high as 518 cm(2)/(V s) which outperforms other devices reported in the literature due to reduced undesirable carrier scattering. In addition, the GeSn N-MOSFETs also exhibit promising characteristics in terms of acceptable subthreshold swing of 156 mV/dec and relatively large I(ON)/I(OFF) ratio more than 4 orders. Moreover, the robust reliability in terms small V(t) variation against high field stress attests the feasibility of using the O2 plasma-treated passivation to advanced GeSn technology.

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications

“…GeSn has an extremely high carrier mobility, so it may also be an ideal materials for transistor applications. Due to the significant development of GeSn CVD growth technology, vertically stacked 3-GeSn-nanosheet pGAAFETs (gate-all-around FETs) [ 91 ], GeSn p-FinFETs [ 92 , 93 ], GeSn n-channel MOSFETs [ 94 , 95 ], GeSn/Ge vertical nanowire pFETs [ 96 ], GeSn GAA nanowire pFETs [ 97 ], and GeSn n-FinFETs [ 98 ] have been successfully demonstrated. Additionally, GeSn’s direct band gap property was found to effectively improve the tunneling probability of electrons, making an excellent material for TFET preparation [ 99 , 100 ], this opening a new development direction for the integrated circuit after Moore’s era.…”

Low Temperature Deposition of High-k/Metal Gate Stacks on High-Sn Content (Si)GeSn-Alloys

“…Transistors (MOSFETs) 10,11 and Tunneling FETs (TFETs) 12,13 have been fabricated and improvements of both, electron and hole mobilities as compared to Ge based devices have been achieved. However, so far mostly binary GeSn layers with low Sn contents under high compressive strain have been used, where the advantages over Ge are limited.…”

Nanoscale n++-p junction formation in GeOI probed by tip-enhanced Raman spectroscopy and conductive atomic force microscopy

“…Moreover, the carrier mobility in Ge can be easily enhanced by alloying Ge with Sn and strain engineering. [7][8][9][10] The Si chemistry and high-k gate oxides can also be adopted for Ge, which makes the integration of Ge with Si even more attractive. The remaining challenges in Ge nanoelectronics are ultrahigh n-type doping and a low specific contact resistance (ρ c ) in n-type Ge.…”