MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.Index Terms-Leakage current, low power, bias temperature instability (NBTI/PBTI), process variation, register file (RF). 1063-8210

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“…The effect of N R size on the wakeup delay is similar to the traditional power gating analysis [32]. This wakeup delay is expressed as…”

Section: Implementation Considerationsmentioning

confidence: 91%

“…17. Accordingly, to achieve optimized power efficiency in heavily multiported RF, the proposed TM-RF can be applied in conjunction with low-power peripheral techniques, such as the MZZ-HVS approach [32].…”

Section: Power Reduction Under Different Rf Configurationsmentioning

confidence: 99%

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Gong

Wang

Jiang

et al. 2015

IEEE Trans. VLSI Syst.

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“…However, on average 25% less energy is consumed where the FLI activates the associated driver, and 57% less energy when the FLI deactivate the associated driver (means the Hob contains narrow-width value) as compared to partitioned word line driver. It is noteworthy that although the area of our proposed driver is more than others, the leakage power reduction caused by the stacking effect [16] of transistors help that the power and energy consumption decrease.…”

Section: Word Line Drivermentioning

confidence: 97%

Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana

Khameneh

Goudarzi

2015

Microprocessors and Microsystems

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“…Depending on the load to drive, a wordline driver essentially is a chain of three to five cascade inverters [10]. Assuming nMOS access transistors in the SRAM cells, to correctly read/write a certain row of the memory, the wordline of the selected row must be asserted to Vdd, whereas the wordlines of the rows not accessed must be tied to GND.…”

Section: Design Of Mixed Single-well Sram Wordline Drivermentioning

confidence: 99%

“…Recently, leakage-reduction techniques for peripheral circuits, such as input buffers, output drivers, and wordline buffers have gained particular interest [10]. It has been noted that such circuits considerably contribute to the overall static power consumption of a SRAM and often their leakage currents exceed that of the cell array.…”

Section: Introductionmentioning

confidence: 99%

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology

Corsonello

Frustaci

Perri

2015

IEEE Trans. VLSI Syst.

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This brief deals with a new design of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. The proposed approach synergistically adopts the poly biasing technique in conjunction with single-well/flip-well configurations and body biasing to opportunely tune the threshold voltage of the devices in the standby and active mode. A tuning methodology is described to optimize the static energy consumption. Post-layout simulations, done at power supply voltages ranging between 1 V and 0.5 V, have shown that, in comparison with the state-of-the-art techniques based on the same UTBB FDSOI technology, the proposed design achieves a maximum leakage up to 85% lower without paying significant delay penalties.Index Terms-Body biasing, leakage optimization, poly biasing, SRAM peripheral, ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI).

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MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits

Cited by 7 publications

References 54 publications

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Dynamically adaptive register file architecture for energy reduction in embedded processors

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology

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