Multiplier‐less pipeline architecture for lifting‐based two‐dimensional discrete wavelet transform

Abstract

In this study, the authors present a multiplier-less, high-speed and low-power pipeline architecture with novel dual Zscanning technique for lifting-based two-dimensional (2D) discrete wavelet transform (DWT). The proposed architecture is composed of pipeline one-dimensional row, column processors and five transposing registers. Moreover, it uses 4N temporal line buffers to process 2D DWT of image with N × N resolution. Multipliers are designed with shift-and-add logic to reduce the critical path to one adder. Dual Z-scanning method is employed to reduce the transposition buffers and latency. The proposed architecture is superior to the existed architectures in speed, power and hardware utilisation for similar throughput specification. Register transfer logic (RTL) of the proposed design is described using VHDL and synthesised using Xilinx ISE 10.1. The proposed architecture operates at a frequency of 353.107 MHz, when synthesised for Xilinx Virtex-IV series field programmable gate array. Frame processing rate of 340 frames/second for full high-definition video can be achieved at this frequency of operation. RTL of the proposed design is synthesised using UMC 180 nm technology complementary metal-oxide semiconductor (CMOS) standard cell library for application specific integrated circuit (ASIC) implementation. ASIC synthesis of 2D DWT core uses 20 358 logic gates and consumes only 20.83 mW power at 100 MHz frequency.

A new discrete wavelet transform appropriate for hardware implementation

“…Because the proposed wavelet has low hardware resource, the critical path latency is low and it is limited just by the latency of an adder, while, in other works, by adding many registers, the latency approaches T m , which is higher than T a . In the architecture given in Darji et al, 55 no multiplier has been used to implement a 9/7 wavelet, but the number of registers is higher than that of the proposed wavelet although its throughput is better. Table 7, the results of FPGA implementation of the proposed wavelet with some other works are compared regardless of their implementation or optimization methods.…”

Hardware Implementation of Audio Watermarking Based on DWT Transform

“…The main objective is to achieve the lower and upper matrices (triangular type) and normalized diagonal matrix by dividing the polyphase matrix of the wavelet filters [19]. As indicated by the fundamental rule, the lifting filter of polyphase matrix of a 9/7 is defined as in Eq.…”

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture

“…Some of the architectures based on parallel lifting scheme [2] with effective memory accessing scheme based on scanning method requires less memory. Architecture based on Zscanning technique [3] presents a multiplier less pipeline architecture to reduce latency and uses a 4N temporal memory. With improvements done to convolution based architectures it provides small overhead of complexity and with no use of temporary registers for storing different values with low area and power reconfigurable architecture [4] using 9/3 and 5/3 filters.…”