A new discrete wavelet transform appropriate for hardware implementation

Distributed arithmetic (DA) is an efficient way to implement sum-of-product units, which can be used in applications such as FIR filters, filter banks, image processing, and convolutional neural networks in IoT hardware accelerators. In this paper, a low-power architecture is offered centered on two key steps, coarse-grain power-performance partitioning and fine-grain separated power supply, and tuned a level shifter in any digital systems implemented based on RTL design. To examine the new design approach, two methods are proposed, at first exploring the power consumption and critical delay path and then separating the power supply of datapath and controller in DA with/without utilizing an implicit level shifter. To investigate power consumption and timing parameters, two 5-tap and 16-tap FIR-filters are implemented in 65-nm CMOS standard technology. In proposed1, dynamic and static power consumption of 16-tap (5-tap) FIR-filter is improved by 30% (15%) and 59% (59%), respectively.Nevertheless, the delay and slope of the generated signal in the shiftreg are significantly increased by reducing the power supply. To tackle this issue, the second method suggested with 26% (14%) improvement in dynamic power and 55% (58%) in static power consumption, which does not increase any delay in the output of shiftreg compared to conventional DA-based FIR filter with solitary power supply.distributed arithmetic, FIR filter, inner product, low-power, power-performance partitioning, RTL design and literature reviewInner product computation is an essential operation in digital signal processing (DSP) applications targeting image, audio, and video processing, as well as various applications of machine learning. 1 It could be used through a common multiply-accumulate (MAC) structure or an improved MAC method called distributed arithmetic (DA) to implement the sum of multiplications. The MAC structure is a high-consumption unit in implementation and not cost-effective in designing high-performance systems due to a large number of multipliers. DA structure is a bit-level rearrangement of

Section: Simulation Resultsmentioning

confidence: 99%

A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

Ghamkhari

Ghaznavi‐Ghoushchi

2021

“…The WT of a function f ( x ) at the scale a and position b is defined by 25

W_{f} ()(, a, b) = \frac{1}{\sqrt{a}} \int_{- \infty}^{\infty} f ()(, t) ψ^{*} ()(, \frac{t - b}{a}) italicdt,

where ψ ( t ) is a wavelet base and * denotes the complex conjugation. According to signal and system theory, the analog computation of W f ( a , b ) can be achieved through the implementation of the linear filter bank of which the impulse response satisfies the following:

h ()(, t) = \frac{1}{\sqrt{a}} ψ ()(, \frac{- t}{a}) .

…”

Section: Rational Approximations Of Gaussian Wavelet Seriesmentioning

confidence: 99%

General rational approximation of Gaussian wavelet series and continuous‐time g_m‐C filter implementation

Sun

2020

Summary A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple gm‐C integrators is presented in this work. Firstly, the multiorder derivatives of Gaussian function are analyzed and proved as wavelet base functions. Then a high‐accuracy general approximation model of Gaussian wavelet series is constructed, and the transfer function of first‐order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a fifth‐order continuous‐time analog first‐order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with a simple gm‐C integrator as the basic blocks. Finally, simulation results demonstrate that the proposed method is an excellent way for the wavelet transform implementation. The designed first‐order derivative of Gaussian wavelet filter circuit operates from a 0.53‐V supply voltage and a bias current 2.5 nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1 nW. Moreover, the high‐accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.

“…Also, nothing was mentioned about the execution time of the EEMD processor. In Meshkat and Dehghani 23 and in Souani et al, 24 hardware implementation of another widely used DSP transform such as discrete wavelet transform (DWT) was proposed.…”

Section: Introductionmentioning

confidence: 99%

Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

Das

Pradhan

2021

Empirical mode decomposition (EMD) is considered as a suitable method when the signal to be analyzed is nonlinear or nonstationary in nature. But, EMD suffers from a problem known as mode mixing. To, reduce this problem, ensemble EMD (EEMD) was proposed. In this paper, we have presented a fast field-programmable gate array (FPGA)-based design for EEMD. Where calculation of output can be done in a parallel manner for different realizations.The design has a comparatively less execution time, and the execution time of the proposed EEMD design is even less than some state-of-the-art EMD-based design, although the architecture of EEMD is more complex, when compared with the EMD design. In this work, we have also performed an FPGA implementation of the EMD algorithm. The root mean square error (RMSE) and the correlation values of the intrinsic mode function (IMFs) obtained from the proposed EMD and EEMD designs are compared. The proposed FPGA-based architecture of the EEMD algorithm is designed using Verilog-hardware description language (HDL) and implemented on a Kintex-7 FPGA. The EEMD architecture consists of cubic Hermite spline interpolation (CHSI) and cubic spline interpolation (CSI) for the envelope generation. K E Y W O R D Sempirical mode decomposition (EMD), ensemble empirical mode decomposition (EEMD), field-programmable gate array (FPGA), parallel architectures