Summary A new method for computation of discrete wavelet transform is introduced. The impulse response of the finite impulse response (FIR) filter, as the main block in filter bank method, is realized such that orthonormal wavelet transform is achieved without using any multiplier as the most challenging part of the FIR filters. It is proved that the calculated Sobolev regularity of the proposed wavelet is higher than that of Daubechies for the same support width. Compared with most popular known wavelets, simulation results of the newly introduced wavelet for signal denoising prove remarkable advantage of our wavelet especially in terms of complexity and power consumption. The proposed wavelet and well‐known Daubechies wavelet are separately implemented on the Spartan‐6 FPGA (Field Programmable Gate Array) to compare the performance of them. The occupied slices and LUTs (Lookup Table) in realization of the proposed wavelet in comparison with those of Daubechies wavelet are decreased by 50% and 56%, respectively. Its power consumption at 100 MHz is also reduced by 86% in comparison with the Daubechies wavelet, and maximum frequency is increased by 186%. Implementation with standard cells of a 0.18‐μm CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor) technology shows 75% and 85% reduction in the power and chip area, respectively.
A fully integrated switched-inductor switched-capacitor (SISC) DC-DC converter is proposed. This converter is designed in such a way that the input voltage can be twice the process allowable voltage without damaging the on-chip transistors. To mitigate large series resistance of on-chip inductors as one of the main challenges in the switched-inductor power supply on chip, two solutions are proposed. By using analytical model of an on-chip inductor, optimal physical dimensions are designed to achieve the desired inductance with minimum series resistance in a small area. Along with the optimization, the dualpath structure of the proposed converter reduces series resistance losses of the on-chip inductor and increases the effective quality factor up to 7 times in duty cycle of 0.8. The proposed converter is implemented in 0.18 μm standard CMOS process. The circuit converts input voltage of 3.6-0.9 V at the load current of 125 mA with the efficiency of 72.8%. Efficiency enhancement factor reaches 72% at 600 mV output voltage. The achieved current density of the proposed converter is 333 mA/mm 2 . By calculating small signal model of the proposed converter and designing a suitable feedback loop, an appropriate transient behavior was provedcascode buck converter, fully integrated voltage regulator, high current density, high stepdown, inductor quality factor boosting, on-chip inductor optimum design
Summary A new method for computation of discrete wavelet transform (DWT) is introduced. The impulse response of the FIR filter, as the main block in filter bank (FB) method, is realized such that orthonormal wavelet transform is achieved without using any multiplier as the most challenging part of the FIR filters. The occupied slices and LUTs in the FPGA realization of the proposed wavelet in comparison with those of Daubechies wavelet are decreased by %50 and %56, respectively.
Fully integrated 750-MHz resonant voltage regulator is presented. Providing soft switching conditions for the transistors has prevented degradation of the converter efficiency at this high switching frequency. High switching frequency has reduced volume of the passive on-chip components and thus increased the converter current density. Due to the limitations of the CMOS processes, control and gate drive circuits are designed to increase chip reliability. One of the major challenges of the fully integrated voltage regulators is the on-chip inductor realization. Based on the mathematical models for inductance and resistance of spiral on-chip inductor, the geometric dimensions of the employed inductor are optimally designed to have maximum quality factor and minimum chip area. The power switches are optimized to achieve maximum efficiency. All post layout parasitic elements of MOSFETs and metal routings including inductive effects are extracted using 3-D EM simulation and finite element method for 0.18-μm standard CMOS technology. Maximum output voltage ripple is 5.2% at maximum load current. Peak efficiency of the proposed on-chip power supply is 82% when input/output voltage is 1.8 V/1.48 V and load current is 120 mA. Maximum value of the efficiency enhancement factor is 42% for output input/voltage of 1.8 V/0.55 V. Current density of the proposed converter is 574 mA/mm 2 . In the worst case, the load step causes an overvoltage/undervoltage smaller than 15.56% at the output voltage. K E Y W O R D Sfully integrated voltage regulator (FIVR), soft switching, resonant DC-DC buck converter, high current density, on-chip inductor optimum design
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