Multiple-process behavioral synthesis for mixed hardware-software systems

Adams, J.K.; Thomas, D.E.

doi:10.1109/isss.1995.520606

Cited by 18 publications

(1 citation statement)

References 8 publications

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“…A "sensitivity" determines the degree of performance improvement every time a process is allocated to a hardware processing element (PE) or a software PE. Further function/process level approaches are: Edwards et al [11] with their profile driven approach, Peng et al [12] using Petri Nets and clustering techniques, Adams et al [15] using code motions between tasks, Chou et al [16] focusing on hardware/software interface synthesis, D'Ambrosio et al [17] using a complex metric to evaluate the feasibility of a possible partition and finally applying a branch-and-bound technique, Carreras et al [18] using an approach based on the LOTOS language, the approach of Ismail et al [19] representing an interactive partitioning tool named Partif, Kalavade et al [20] using a two-phase objective function the "GCLD" approach, Sciuto et al [21] deploying a greedy algorithm that partitions Occam II applications, and Teich et al [22] an evolutionary approach. The codesign approaches [29]- [31] do not focus on automated partitioning but concentrate on the cosimulation and/or rapid prototyping issues.…”

Section: Related Workmentioning

confidence: 99%

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Henkel¹,

Ernst

2001

IEEE Trans. VLSI Syst.

115

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Hardware/software partitioning is a key issue in the design of embedded systems when performance constraints have to be met and chip area and/or power dissipation are critical. For that reason, diverse approaches to automatic hardware/software partitioning have been proposed since the early 1990s. In all approaches so far, the granularity during partitioning is fixed, i.e., either small system parts (e.g., base blocks) or large system parts (e.g., whole functions/processes) can be swapped at once during partitioning in order to find the best hardware/software tradeoff. Since the deployment of a fixed granularity is likely to result in suboptimum solutions, we present the first approach that features a flexible granularity during hardware/software partitioning. Our approach is comprehensive in so far that the estimation techniques, our multigranularity performance estimation technique described here in detail, that control partitioning, are adapted to the flexible partitioning granularity. In addition, our multilevel objective function is described. It allows us to tradeoff various design constraints/goals (performance/hardware area) against each other. As a result, our approach is applicable to a wider range of applications than approaches with a fixed granularity. We also show that our approach is fast and that the obtained hardware/software partitions are much more efficient (in terms of hardware effort, for example) than in cases where a fixed granularity is deployed.

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Section: Related Workmentioning

confidence: 99%

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Henkel¹,

Ernst

2001

IEEE Trans. VLSI Syst.

115

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Strategy for power-efficient design of parallel systems

Danckaert

Masselos

Cathoor

et al. 1999

IEEE Trans. VLSI Syst.

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Application studies in the areas of image and video processing indicate that between 50 and 80% of the power cost in these systems is due to data storage and transfers. This is especially true for multi-processor realizations, because conventional parallelization methods ignore the power cost and focus only on performance. However, also the power consumption depends heavily on the way a system is parallelized. To reduce this dominant cost, we propose to address the system-level storage organization for the multi-dimensional signals as a first step in mapping these applications, before the parallelization or partitioning decisions (in particular before the SW/HW partitioning which is traditionally done too early in the design trajectory). Our methodology is illustrated on a parallel QSDPCM video codec.

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Loop pipelining in hardware-software partitioning

Jeon

Choi

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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This paper presents a hardware-software partitioning algorithm that exploits a loop pipelining technique. The partitioning algorithm is based on iterative improvement. The algorithm tries to minimize hardware cost through hardware sharing and hardware implementation selection without violating given performance constraint. The proposed loop pipelining technique, which is an adaptation of a compiler optimization technique for instruction level parallelism, increases parallelism within a loop by transforming the structure of an input system description. By combining this technique with our partitioning algorithm, we can further reduce the hardware cost and/or improve the performance of the partitioned system. Experiments show about 19% performance improvement and 44% reduced hardware for a JPEG encoder design, compared to the results without loop pipelining.

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Multiple-process behavioral synthesis for mixed hardware-software systems

Cited by 18 publications

References 8 publications

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Strategy for power-efficient design of parallel systems

Loop pipelining in hardware-software partitioning

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