Application studies in the areas of image and video processing indicate that between 50 and 80% of the power cost in these systems is due to data storage and transfers. This is especially true for multi-processor realizations, because conventional parallelization methods ignore the power cost and focus only on performance. However, also the power consumption depends heavily on the way a system is parallelized. To reduce this dominant cost, we propose to address the system-level storage organization for the multi-dimensional signals as a first step in mapping these applications, before the parallelization or partitioning decisions (in particular before the SW/HW partitioning which is traditionally done too early in the design trajectory). Our methodology is illustrated on a parallel QSDPCM video codec.

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Traditionally, engineers design for the worst case scenario but in most cases the maximum performance is not required so that there is an important waste of energy consumption. Developers should design systems for different power consumption versus execution time tradeoffs. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can reach different computational/power trades offs points and thus design power efficient platforms. In this paper, we present a high level methodology to get an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a C++ description of a MPEG-4 encoder which is translated to a SystemC implementation which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a typical DSP.

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