An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques

Abstract

Hardware/software partitioning is a key issue in the design of embedded systems when performance constraints have to be met and chip area and/or power dissipation are critical. For that reason, diverse approaches to automatic hardware/software partitioning have been proposed since the early 1990s. In all approaches so far, the granularity during partitioning is fixed, i.e., either small system parts (e.g., base blocks) or large system parts (e.g., whole functions/processes) can be swapped at once during partitioning in order to find the best hardware/software tradeoff. Since the deployment of a fixed granularity is likely to result in suboptimum solutions, we present the first approach that features a flexible granularity during hardware/software partitioning. Our approach is comprehensive in so far that the estimation techniques, our multigranularity performance estimation technique described here in detail, that control partitioning, are adapted to the flexible partitioning granularity. In addition, our multilevel objective function is described. It allows us to tradeoff various design constraints/goals (performance/hardware area) against each other. As a result, our approach is applicable to a wider range of applications than approaches with a fixed granularity. We also show that our approach is fast and that the obtained hardware/software partitions are much more efficient (in terms of hardware effort, for example) than in cases where a fixed granularity is deployed.

Hardware–software co-design of an iris recognition algorithm

“…In the partitioning process, parts of the software application whose sizes depend on the granularity of the partitioning are moved to hardware until constraints are met. Conversely, in a hardware-oriented approach the migration is done in the reverse direction, from hardware to software [17]. In our particular case, given that the whole algorithm exists in ANSI C, the partitioning process is undertaken with a software-oriented approach.…”

Finding optimal hardware/software partitions

“…In particular, genetic algorithms have been extensively used [3,12,34,41,44], as well as simulated annealing [13,14,15,20,28]. Other, less popular heuristics in this group are tabu search [13,14] and greedy algorithms [10,17].…”

“…the semantics of a node. There have been works on low granularity, where a node represents a single instruction or a short sequence of instructions [6,8,40,21], middle granularity, where a node represents a basic block [22,27,38], and high granularity, where a node represents a function or procedure [18,36,48,2], as well as flexible granularity, where a node can represent any of the above [20,47].…”

“…In a number of related papers, the target architecture is supposed to consist of a single software and a single hardware unit [13,17,18,20,31,32,34,37,40,44,45,49], whereas others do not impose this limitation [10,12,25,36]. Some limit parallelism inside hardware or software [44,49] or between hardware and software [20,32].…”

“…Some limit parallelism inside hardware or software [44,49] or between hardware and software [20,32]. The system to be partitioned is usually given in the form of a task graph, or a set of task graphs, usually assumed to be directed acyclic graphs describing the dependencies between the components of the system.…”