Multidimensional DSP Core Synthesis for FPGA

Abstract

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense.

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs

“…Previous work on mapping dataflow structures into hardware include the work on VLSI dataflow arrays [12], SystemC [13], and multidimensional arrayed dataflow [14]. The methods developed in this paper are different from these approaches in their support for parameterized dataflow modeling, and the novel features of dynamic parameter reconfiguration and reconfigurable dataflow modeling that are provided by PSDF semantics [8].…”

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

“…McAllister et al [10] considered various implementations of a multi-dimensional SDF graph including hybrid implementation in targeting a reconfigurable device (e.g. FPGA).…”

“…1e is also explored, which is not considered in the previous approaches. The hybrid execution is taken into account in [10] under schedule restriction. But, their focus is different from ours in that they mainly concern the core (SDF node) generation only while we are also considering the efficient control logic generation.…”

Model-based mapping of reconfigurable image registration on FPGA platforms

“…In [22], the authors present a system design approach using a different model, called the Kahn process network model, which can be used to generate RTL code for applications written in MATLAB to be automatically mapped onto FPGA-and microprocessor-based platforms. In [14], the authors propose a heterogeneous system modeling approach based on dataflow graphs for synthesis on FPGAs. This approach focuses mainly on core generation for reusability.…”